diff -urN linux-2.6.11-rc5.orig/arch/arm/Kconfig linux-2.6.11-rc5/arch/arm/Kconfig
--- linux-2.6.11-rc5.orig/arch/arm/Kconfig	Fri Feb 25 11:51:20 2005
+++ linux-2.6.11-rc5/arch/arm/Kconfig	Fri Feb 25 11:55:46 2005
@@ -179,6 +179,12 @@
 	help
 	  This enables support for systems based on the Hynix HMS720x
 
+config ARCH_AT91RM9200
+	bool "AT91RM9200"
+	help
+	  Say Y here if you intend to run this kernel on an AT91RM9200-based
+	  board.
+
 endchoice
 
 source "arch/arm/mach-clps711x/Kconfig"
@@ -211,6 +217,8 @@
 
 source "arch/arm/mach-versatile/Kconfig"
 
+source "arch/arm/mach-at91rm9200/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
 	bool
@@ -618,7 +626,7 @@
 
 config LEDS
 	bool "Timer and CPU usage LEDs"
-	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE || ARCH_IMX
+	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE || ARCH_IMX || ARCH_AT91RM9200
 	help
 	  If you say Y here, the LEDs on your machine will be used
 	  to provide useful information about your current system status.
@@ -631,8 +639,8 @@
 	  system, but the driver will do nothing.
 
 config LEDS_TIMER
-	bool "Timer LED" if LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || MACH_MAINSTONE || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE || ARCH_IMX || MACH_OMAP_H2 || MACH_OMAP_PERSEUS2)
-	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE || ARCH_IMX
+	bool "Timer LED" if LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || MACH_MAINSTONE || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE || ARCH_IMX || MACH_OMAP_H2 || MACH_OMAP_PERSEUS2 || ARCH_AT91RM9200)
+	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE || ARCH_IMX || ARCH_AT91RM9200
 	default y if ARCH_EBSA110
 	help
 	  If you say Y here, one of the system LEDs (the green one on the
@@ -647,7 +655,7 @@
 
 config LEDS_CPU
 	bool "CPU usage LED"
-	depends on LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE || ARCH_IMX || MACH_OMAP_H2 || MACH_OMAP_PERSEUS2)
+	depends on LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE || ARCH_IMX || MACH_OMAP_H2 || MACH_OMAP_PERSEUS2 || ARCH_AT91RM9200)
 	help
 	  If you say Y here, the red LED will be used to give a good real
 	  time indication of CPU usage, by lighting whenever the idle task
diff -urN linux-2.6.11-rc5.orig/arch/arm/Makefile linux-2.6.11-rc5/arch/arm/Makefile
--- linux-2.6.11-rc5.orig/arch/arm/Makefile	Fri Feb 25 11:50:10 2005
+++ linux-2.6.11-rc5/arch/arm/Makefile	Fri Feb 25 11:55:46 2005
@@ -99,6 +99,7 @@
  machine-$(CONFIG_ARCH_VERSATILE)  := versatile
  machine-$(CONFIG_ARCH_IMX)	   := imx
  machine-$(CONFIG_ARCH_H720X)	   := h720x
+ machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
diff -urN linux-2.6.11-rc5.orig/arch/arm/boot/compressed/Makefile linux-2.6.11-rc5/arch/arm/boot/compressed/Makefile
--- linux-2.6.11-rc5.orig/arch/arm/boot/compressed/Makefile	Fri Feb 25 11:51:20 2005
+++ linux-2.6.11-rc5/arch/arm/boot/compressed/Makefile	Fri Feb 25 11:55:46 2005
@@ -50,6 +50,10 @@
 OBJS		+= head-sharpsl.o
 endif
 
+ifeq ($(CONFIG_ARCH_AT91RM9200),y)
+OBJS		+= head-at91rm9200.o
+endif
+
 ifeq ($(CONFIG_DEBUG_ICEDCC),y)
 OBJS            += ice-dcc.o
 endif
diff -urN linux-2.6.11-rc5.orig/arch/arm/boot/compressed/head-at91rm9200.S linux-2.6.11-rc5/arch/arm/boot/compressed/head-at91rm9200.S
--- linux-2.6.11-rc5.orig/arch/arm/boot/compressed/head-at91rm9200.S	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/boot/compressed/head-at91rm9200.S	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,15 @@
+/*
+ * linux/arch/arm/boot/compressed/head-at91rm9200.S
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <asm/mach-types.h>
+
+		.section	".start", "ax"
+		mov	r7, #MACH_TYPE_AT91RM9200
diff -urN linux-2.6.11-rc5.orig/arch/arm/boot/compressed/head.S linux-2.6.11-rc5/arch/arm/boot/compressed/head.S
--- linux-2.6.11-rc5.orig/arch/arm/boot/compressed/head.S	Fri Feb 25 11:50:10 2005
+++ linux-2.6.11-rc5/arch/arm/boot/compressed/head.S	Fri Feb 25 11:55:46 2005
@@ -125,6 +125,15 @@
 		.macro	writeb, rb
 		strb	\rb, [r3, #0x20]
 		.endm
+#elif defined(CONFIG_ARCH_AT91RM9200)
+		.macro	loadsp, rb
+		mov	\rb, #0xFF000000	@ BASE_DBGU (we cannot use ldr \reg, =AT91_DBGU_BASE)
+		add	\rb, \rb, #0x00FF0000
+		add	\rb, \rb, #0x0000F200
+		.endm
+		.macro	writeb, rb
+		strb	\rb, [r3, #0x1C]	@ DBGU_THR (Transmitter Holding Register)
+		.endm
 #else
 #error no serial architecture defined
 #endif
diff -urN linux-2.6.11-rc5.orig/arch/arm/configs/at91rm9200dk_defconfig linux-2.6.11-rc5/arch/arm/configs/at91rm9200dk_defconfig
--- linux-2.6.11-rc5.orig/arch/arm/configs/at91rm9200dk_defconfig	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/configs/at91rm9200dk_defconfig	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,833 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.11-rc3
+# Fri Feb 11 11:51:15 2005
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_IOMAP=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_H720X is not set
+CONFIG_ARCH_AT91RM9200=y
+
+#
+# AT91RM9200 Implementations
+#
+CONFIG_ARCH_AT91RM9200DK=y
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+
+#
+# General setup
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_XIP_KERNEL is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+# CONFIG_LEDS_CPU is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_PARTITIONS is not set
+# CONFIG_MTD_CONCAT is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_AMDSTD_RETRY=0
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x10000000
+CONFIG_MTD_PHYSMAP_LEN=0x200000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_EDB7312 is not set
+# CONFIG_MTD_IMPA7 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_AT91_DATAFLASH=y
+CONFIG_MTD_AT91_DATAFLASH_CARD=y
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+CONFIG_ARM_AT91_ETHER_RMII=y
+# CONFIG_SMC91X is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_AT91=y
+CONFIG_SERIAL_AT91_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+CONFIG_AT91_SPI=y
+CONFIG_AT91_SPIDEV=y
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_AT91=y
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Hardware Sensors Chip support
+#
+# CONFIG_I2C_SENSOR is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_EXPORTFS is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+
+#
+# USB Host Controller Drivers
+#
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_BLUETOOTH_TTY is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_EGALAX is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETKIT is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB ATM/DSL drivers
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_FS is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
diff -urN linux-2.6.11-rc5.orig/arch/arm/configs/csb337_defconfig linux-2.6.11-rc5/arch/arm/configs/csb337_defconfig
--- linux-2.6.11-rc5.orig/arch/arm/configs/csb337_defconfig	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/configs/csb337_defconfig	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,854 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.10
+# Tue Feb  1 12:57:06 2005
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_IOMAP=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION="-csb"
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_H720X is not set
+CONFIG_ARCH_AT91RM9200=y
+
+#
+# AT91RM9200 Implementations
+#
+# CONFIG_ARCH_AT91RM9200DK is not set
+CONFIG_MACH_CSB337=y
+# CONFIG_MACH_CSB637 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+
+#
+# General setup
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_XIP_KERNEL is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_ARM_AT91_ETHER_RMII is not set
+# CONFIG_SMC91X is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+# CONFIG_BLK_DEV_SD is not set
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_AT91=y
+CONFIG_SERIAL_AT91_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_AT91_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+CONFIG_AT91_SPI=y
+CONFIG_AT91_SPIDEV=y
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_AT91=y
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Hardware Sensors Chip support
+#
+# CONFIG_I2C_SENSOR is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+CONFIG_DS1307=y
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+
+#
+# USB Host Controller Drivers
+#
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_BLUETOOTH_TTY is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_RW_DETECT is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_EGALAX is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+CONFIG_USB_SERIAL_KEYSPAN=y
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+CONFIG_USB_SERIAL_MCT_U232=y
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+CONFIG_USB_EZUSB=y
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_TIGL is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETKIT is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB ATM/DSL drivers
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
diff -urN linux-2.6.11-rc5.orig/arch/arm/configs/csb637_defconfig linux-2.6.11-rc5/arch/arm/configs/csb637_defconfig
--- linux-2.6.11-rc5.orig/arch/arm/configs/csb637_defconfig	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/configs/csb637_defconfig	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,854 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.10
+# Tue Feb  1 13:10:16 2005
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_IOMAP=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION="-csb"
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_H720X is not set
+CONFIG_ARCH_AT91RM9200=y
+
+#
+# AT91RM9200 Implementations
+#
+# CONFIG_ARCH_AT91RM9200DK is not set
+# CONFIG_MACH_CSB337 is not set
+CONFIG_MACH_CSB637=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+
+#
+# General setup
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_XIP_KERNEL is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_ARM_AT91_ETHER_RMII is not set
+# CONFIG_SMC91X is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+# CONFIG_BLK_DEV_SD is not set
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_AT91=y
+CONFIG_SERIAL_AT91_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_AT91_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+CONFIG_AT91_SPI=y
+CONFIG_AT91_SPIDEV=y
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_AT91=y
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Hardware Sensors Chip support
+#
+# CONFIG_I2C_SENSOR is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+CONFIG_DS1307=y
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+
+#
+# USB Host Controller Drivers
+#
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_BLUETOOTH_TTY is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_RW_DETECT is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_EGALAX is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+CONFIG_USB_SERIAL_KEYSPAN=y
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+CONFIG_USB_SERIAL_MCT_U232=y
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+CONFIG_USB_EZUSB=y
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_TIGL is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETKIT is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB ATM/DSL drivers
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
diff -urN linux-2.6.11-rc5.orig/arch/arm/kernel/irq.c linux-2.6.11-rc5/arch/arm/kernel/irq.c
--- linux-2.6.11-rc5.orig/arch/arm/kernel/irq.c	Fri Feb 25 11:51:20 2005
+++ linux-2.6.11-rc5/arch/arm/kernel/irq.c	Fri Feb 25 11:55:46 2005
@@ -56,6 +56,13 @@
 void (*init_arch_irq)(void) __initdata = NULL;
 
 /*
+ * No architecture-specific irq_finish function defined in arm/arch/irqs.h.
+ */
+#ifndef irq_finish
+#define irq_finish(irq) do { } while (0)
+#endif
+
+/*
  * Dummy mask/unmask handler
  */
 void dummy_mask_unmask_irq(unsigned int irq)
@@ -532,6 +539,8 @@
 	if (!list_empty(&irq_pending))
 		do_pending_irqs(regs);
 
+	irq_finish(irq);
+
 	spin_unlock(&irq_controller_lock);
 	irq_exit();
 }
diff -urN linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/Kconfig linux-2.6.11-rc5/arch/arm/mach-at91rm9200/Kconfig
--- linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/Kconfig	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/mach-at91rm9200/Kconfig	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,31 @@
+if ARCH_AT91RM9200
+
+menu "AT91RM9200 Implementations"
+
+choice
+	prompt "Select AT91RM9200-based board"
+	default MACH_AT91RM9200DK
+
+config ARCH_AT91RM9200DK
+	bool "Atmel AT91RM9200-DK Development board"
+	depends on ARCH_AT91RM9200
+	help
+	  Select this if you are using Atmel's AT91RM9200-DK Development board
+
+config MACH_CSB337
+	bool "Cogent CSB337 board"
+	depends on ARCH_AT91RM9200
+	help
+	  Select this if you are using Cogent's CSB337 board
+
+config MACH_CSB637
+	bool "Cogent CSB637 board"
+	depends on ARCH_AT91RM9200
+	help
+	  Select this if you are using Cogent's CSB637 board
+
+endchoice
+
+endmenu
+
+endif
diff -urN linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/Makefile linux-2.6.11-rc5/arch/arm/mach-at91rm9200/Makefile
--- linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/Makefile	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/mach-at91rm9200/Makefile	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,15 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y			:= core.o time.o
+obj-m			:=
+obj-n			:=
+obj-			:=
+
+# LEDs support
+leds-$(CONFIG_ARCH_AT91RM9200DK) += dk-leds.o
+leds-$(CONFIG_MACH_CSB337) += dk-leds.o
+leds-$(CONFIG_MACH_CSB637) += dk-leds.o
+obj-$(CONFIG_LEDS) += $(leds-y)
+
diff -urN linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/Makefile.boot linux-2.6.11-rc5/arch/arm/mach-at91rm9200/Makefile.boot
--- linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/Makefile.boot	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/mach-at91rm9200/Makefile.boot	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,11 @@
+# Note: the following conditions must always be true:
+#   ZRELADDR == virt_to_phys(TEXTADDR)
+#   PARAMS_PHYS must be within 4MB of ZRELADDR
+#   INITRD_PHYS must be in RAM
+
+   zreladdr-y   := 0x20008000
+params_phys-y	:= 0x20000100
+initrd_phys-y	:= 0x20410000
+
+#params_phys-y   := 0x00000100
+#initrd_phys-y   := 0x00800000
diff -urN linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/core.c linux-2.6.11-rc5/arch/arm/mach-at91rm9200/core.c
--- linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/core.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/mach-at91rm9200/core.c	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,196 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/core.c
+ *
+ *  Copyright (c) 2004 SAN People
+ *  Copyright (c) 2004 ATMEL
+ *  Copyright (c) Rick Bronson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/platform.h>
+#include <asm/mach/serial_at91rm9200.h>
+
+#include "generic.h"
+
+/*
+ * System peripheral registers mapped at virtual address.
+ */
+AT91PS_SYS AT91_SYS = (AT91PS_SYS) AT91C_VA_BASE_SYS;
+EXPORT_SYMBOL(AT91_SYS);   
+
+static struct map_desc at91rm9200_io_desc[] __initdata = {
+	/* virtual,             physical,          length,   type */
+	{ AT91C_VA_BASE_SYS,    AT91C_BASE_SYS,    SZ_4K,    MT_DEVICE},
+	{ AT91C_VA_BASE_SPI,    AT91C_BASE_SPI,    SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_SSC2,   AT91C_BASE_SSC2,   SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_SSC1,   AT91C_BASE_SSC1,   SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_SSC0,   AT91C_BASE_SSC0,   SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_US3,    AT91C_BASE_US3,    SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_US2,    AT91C_BASE_US2,    SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_US1,    AT91C_BASE_US1,    SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_US0,    AT91C_BASE_US0,    SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_EMAC,   AT91C_BASE_EMAC,   SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_TWI,    AT91C_BASE_TWI,    SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_MCI,    AT91C_BASE_MCI,    SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_UDP,    AT91C_BASE_UDP,    SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_TCB1,   AT91C_BASE_TCB1,   SZ_16K,   MT_DEVICE},
+	{ AT91C_VA_BASE_TCB0,   AT91C_BASE_TCB0,   SZ_16K,   MT_DEVICE}
+};
+
+/* Interrupt configuration */
+static AT91_REG at91rm9200_irq_smr[] __initdata = {
+	(AT91_SMR_FIQ),		/* FIQ */
+	(AT91_SMR_SYS),		/* System Peripherals */
+	(AT91_SMR_PIOA),	/* PIO A */
+	(AT91_SMR_PIOB),	/* PIO B */
+	(AT91_SMR_PIOC),	/* PIO C */
+	(AT91_SMR_PIOD),	/* PIO D */
+	(AT91_SMR_US0),		/* USART 0 */
+	(AT91_SMR_US1),		/* USART 1 */
+	(AT91_SMR_US2),		/* USART 2 */
+	(AT91_SMR_US3),		/* USART 3 */
+	(AT91_SMR_MCI),		/* Multimedia Card */
+	(AT91_SMR_UDP),		/* USB Device */
+	(AT91_SMR_TWI),		/* Two-wire interface */
+	(AT91_SMR_SPI),		/* SPI */
+	(AT91_SMR_SSC0),	/* Sync Serial 0 */
+	(AT91_SMR_SSC1),	/* Sync Serial 1 */
+	(AT91_SMR_SSC2),	/* Sync Serial 2 */
+	(AT91_SMR_TC0),		/* TC 0 */
+	(AT91_SMR_TC1),		/* TC 1 */
+	(AT91_SMR_TC2),		/* TC 2 */
+	(AT91_SMR_TC3),		/* TC 3 */
+	(AT91_SMR_TC4),		/* TC 4 */
+	(AT91_SMR_TC5),		/* TC 5 */
+	(AT91_SMR_UHP),		/* USB Host */
+	(AT91_SMR_EMAC),	/* Ethernet */
+	(AT91_SMR_IRQ0),	/* IRQ 0 */
+	(AT91_SMR_IRQ1),	/* IRQ 1 */
+	(AT91_SMR_IRQ2),	/* IRQ 2 */
+	(AT91_SMR_IRQ3),	/* IRQ 3 */
+	(AT91_SMR_IRQ4),	/* IRQ 4 */
+	(AT91_SMR_IRQ5),	/* IRQ 5 */
+	(AT91_SMR_IRQ6)		/* IRQ 6 */
+};
+
+/* Architecture-specific fixups */
+static void __init at91rm9200_fixup(struct machine_desc *desc, struct tag *tags,
+		 char **cmdline, struct meminfo *mi)
+{
+
+}
+
+void __init at91rm9200_map_io(void)
+{
+	int serial[AT91C_NR_UART] = AT91C_UART_MAP;
+	int i;
+
+	iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
+
+#ifdef CONFIG_SERIAL_AT91
+	/* Register UARTs */
+	for (i = 0; i < AT91C_NR_UART; i++) {
+		if (serial[i] >= 0)
+			at91_register_uart(i, serial[i]);
+	}
+#endif
+}
+
+static void __init at91rm9200_init_machine(void)
+{
+	platform_add_devices(at91rm9200_devices, ARRAY_SIZE(at91rm9200_devices));
+}
+
+static void at91rm9200_mask_irq(unsigned int irq)
+{
+	/* Disable interrupt on AIC */
+	AT91_SYS->AIC_IDCR =  1 << irq;
+}
+
+static void at91rm9200_unmask_irq(unsigned int irq)
+{
+	/* Enable interrupt on AIC */
+	AT91_SYS->AIC_IECR =  1 << irq;
+}
+
+static struct irqchip at91rm9200_irq_chip = {
+	.ack	= at91rm9200_mask_irq,
+	.mask	= at91rm9200_mask_irq,
+	.unmask	= at91rm9200_unmask_irq,
+};
+
+void __init at91rm9200_init_irq(void)
+{
+	unsigned int i;
+
+	/*
+	 * The IVR is used by macro get_irqnr_and_base to read and verify.
+	 * The irq number is NR_IRQS when a spurious interrupt has occured.
+	 */
+	for (i = 0; i < NR_IRQS; i++) {
+		/* Put irq number in Source Vector Register: */
+		AT91_SYS->AIC_SVR[i] = i;
+		/* Store the Source Mode Register as defined in table above */
+		AT91_SYS->AIC_SMR[i] = at91rm9200_irq_smr[i];
+
+		set_irq_chip(i, &at91rm9200_irq_chip);
+		set_irq_handler(i, do_level_IRQ);
+		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+
+		/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
+		if (i < 8)
+			AT91_SYS->AIC_EOICR = AT91_SYS->AIC_EOICR;
+	}
+
+	/* Spurious Interrupt ID in Spurious Vector Register is NR_IRQS
+	 * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
+	 */
+	AT91_SYS->AIC_SPU = NR_IRQS;
+
+	/* No debugging in AIC: Debug (Protect) Control Register */
+	AT91_SYS->AIC_DCR = 0;
+
+	/* Disable and clear all interrupts initially */
+	AT91_SYS->AIC_IDCR = 0xFFFFFFFF;
+	AT91_SYS->AIC_ICCR = 0xFFFFFFFF;
+}
+
+MACHINE_START(AT91RM9200, "ATMEL AT91RM9200")
+	MAINTAINER("SAN People / ATMEL")
+	BOOT_MEM(AT91_SDRAM_BASE, AT91C_BASE_SYS, AT91C_VA_BASE_SYS)
+	BOOT_PARAMS(AT91_SDRAM_BASE + 0x100)
+	FIXUP(at91rm9200_fixup)
+	MAPIO(at91rm9200_map_io)
+	.timer		= &at91rm9200_timer,
+	INITIRQ(at91rm9200_init_irq)
+	INIT_MACHINE(at91rm9200_init_machine)
+MACHINE_END
diff -urN linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/dk-leds.c linux-2.6.11-rc5/arch/arm/mach-at91rm9200/dk-leds.c
--- linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/dk-leds.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/mach-at91rm9200/dk-leds.c	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,97 @@
+/*
+ * LED driver for the Atmel AT91RM9200 Development Kit.
+ *
+ * (c) SAN People (Pty) Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+*/
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <asm/mach-types.h>
+#include <asm/leds.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pio.h>
+
+
+static inline void at91_led_on(void)
+{
+	AT91_SYS->PIOB_CODR = AT91C_PIO_PB2;
+}
+
+static inline void at91_led_off(void)
+{
+	AT91_SYS->PIOB_SODR = AT91C_PIO_PB2;
+}
+
+static inline void at91_led_toggle(void)
+{
+	unsigned long curr = AT91_SYS->PIOB_ODSR;
+	if (curr & AT91C_PIO_PB2)
+		AT91_SYS->PIOB_CODR = AT91C_PIO_PB2;
+	else
+		AT91_SYS->PIOB_SODR = AT91C_PIO_PB2;
+}
+
+
+/*
+ * Handle LED events.
+ */
+static void at91rm9200dk_leds_event(led_event_t evt)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	
+	switch(evt) {
+	case led_start:		/* System startup */
+		at91_led_on();
+		break;
+
+	case led_stop:		/* System stop / suspend */
+		at91_led_off();
+		break;
+
+#ifdef CONFIG_LEDS_TIMER
+	case led_timer:		/* Every 50 timer ticks */
+		at91_led_toggle();
+		break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+	case led_idle_start:	/* Entering idle state */
+		at91_led_off();
+		break;
+
+	case led_idle_end:	/* Exit idle state */
+		at91_led_on();
+		break;
+#endif
+
+	default:
+		break;
+	}
+	
+	local_irq_restore(flags);
+}
+
+
+static int __init leds_init(void)
+{
+	/* Enable PIO to access the LEDs */
+	AT91_SYS->PIOB_PER = AT91C_PIO_PB2;
+	AT91_SYS->PIOB_OER = AT91C_PIO_PB2;
+
+	leds_event = at91rm9200dk_leds_event;
+
+	leds_event(led_start);
+	return 0;
+}
+
+__initcall(leds_init);
diff -urN linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/generic.h linux-2.6.11-rc5/arch/arm/mach-at91rm9200/generic.h
--- linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/generic.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/mach-at91rm9200/generic.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,13 @@
+/*
+ *  linux/arch/arm/mach-at91rm9200/generic.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extern void __init at91rm9200_map_io(void);
+extern void __init at91rm9200_init_irq(void);
+
+struct sys_timer;
+extern struct sys_timer at91rm9200_timer;
diff -urN linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/time.c linux-2.6.11-rc5/arch/arm/mach-at91rm9200/time.c
--- linux-2.6.11-rc5.orig/arch/arm/mach-at91rm9200/time.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/arch/arm/mach-at91rm9200/time.c	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,126 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/time.c
+ *
+ *  Copyright (C) 2003 SAN People
+ *  Copyright (C) 2003 ATMEL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/time.h>
+
+/*
+ * The ST_CRTR is updated asynchronously to the master clock.  It is therefore
+ *  necessary to read it twice (with the same value) to ensure accuracy.
+ */ 
+static inline unsigned long read_CRTR(void) {
+	unsigned long x1, x2;
+
+	do {
+		x1 = AT91_SYS->ST_CRTR;
+		x2 = AT91_SYS->ST_CRTR;
+	} while (x1 != x2);
+
+	return x1;
+}
+
+/*
+ * Returns number of microseconds since last timer interrupt.  Note that interrupts
+ * will have been disabled by do_gettimeofday()
+ *  'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ *  'tick' is usecs per jiffy (linux/timex.h).
+ */
+static unsigned long at91rm9200_gettimeoffset(void)
+{
+	unsigned long elapsed;
+
+	elapsed = (read_CRTR() - AT91_SYS->ST_RTAR) & AT91C_ST_ALMV;
+
+	return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
+}
+
+/*
+ * IRQ handler for the timer.
+ */
+static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	if (AT91_SYS->ST_SR & AT91C_ST_PITS) {	/* This is a shared interrupt */
+		write_seqlock(&xtime_lock);
+
+		do {
+			timer_tick(regs);
+			AT91_SYS->ST_RTAR = (AT91_SYS->ST_RTAR + LATCH) & AT91C_ST_ALMV;
+		} while (((read_CRTR() - AT91_SYS->ST_RTAR) & AT91C_ST_ALMV) >= LATCH);
+
+		write_sequnlock(&xtime_lock);
+
+		return IRQ_HANDLED;
+	}
+	else
+		return IRQ_NONE;		/* not handled */
+}
+
+static struct irqaction at91rm9200_timer_irq = {
+	.name		= "AT91RM9200 Timer Tick",
+	.flags		= SA_SHIRQ | SA_INTERRUPT,
+	.handler	= at91rm9200_timer_interrupt
+};
+
+/*
+ * Set up timer interrupt.
+ */
+void __init at91rm9200_timer_init(void)
+{
+	/* Disable all timer interrupts */
+	AT91_SYS->ST_IDR = AT91C_ST_PITS | AT91C_ST_WDOVF | AT91C_ST_RTTINC | AT91C_ST_ALMS;
+	(void) AT91_SYS->ST_SR;		/* Clear any pending interrupts */
+
+	// TODO: Get the current time from the RTC.
+
+	/*
+	 * Make IRQs happen for the system timer.
+	 */
+	setup_irq(AT91C_ID_SYS, &at91rm9200_timer_irq);
+
+	/* Set initial alarm to 0 */
+	AT91_SYS->ST_RTAR = 0;
+
+	/* Real time counter incremented every 30.51758 microseconds */
+	AT91_SYS->ST_RTMR = 1;
+
+	/* Set Period Interval timer */
+	AT91_SYS->ST_PIMR = LATCH;
+
+	/* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */
+	tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE;
+
+	/* Enable Period Interval Timer interrupt */
+	AT91_SYS->ST_IER = AT91C_ST_PITS;
+}
+
+struct sys_timer at91rm9200_timer = {
+	.init		= at91rm9200_timer_init,
+	.offset		= at91rm9200_gettimeoffset,
+};
diff -urN linux-2.6.11-rc5.orig/arch/arm/mm/Kconfig linux-2.6.11-rc5/arch/arm/mm/Kconfig
--- linux-2.6.11-rc5.orig/arch/arm/mm/Kconfig	Fri Feb 25 11:51:21 2005
+++ linux-2.6.11-rc5/arch/arm/mm/Kconfig	Fri Feb 25 11:55:46 2005
@@ -62,8 +62,8 @@
 # ARM920T
 config CPU_ARM920T
 	bool "Support ARM920T processor" if !ARCH_S3C2410
-	depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX
-	default y if ARCH_S3C2410
+	depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AT91RM9200
+	default y if ARCH_S3C2410 || ARCH_AT91RM9200
 	select CPU_32v4
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
diff -urN linux-2.6.11-rc5.orig/drivers/char/Kconfig linux-2.6.11-rc5/drivers/char/Kconfig
--- linux-2.6.11-rc5.orig/drivers/char/Kconfig	Fri Feb 25 11:51:32 2005
+++ linux-2.6.11-rc5/drivers/char/Kconfig	Fri Feb 25 11:55:46 2005
@@ -991,5 +991,21 @@
 	  The mmtimer device allows direct userspace access to the
 	  Altix system timer.
 
+config AT91_SPI
+	bool "SPI driver for AT91 processors"
+	depends on ARCH_AT91RM9200
+	default y
+	help
+	  The SPI driver gives access to this serial bus on the AT91x 
+	  processor
+
+config AT91_SPIDEV
+	bool "SPI device interface for AT91 processors"
+	depends on ARCH_AT91RM9200 && AT91_SPI
+	default n
+	help
+	  The SPI driver gives user mode access to this serial 
+	  bus on the AT91x processor
+
 endmenu
 
diff -urN linux-2.6.11-rc5.orig/drivers/char/Makefile linux-2.6.11-rc5/drivers/char/Makefile
--- linux-2.6.11-rc5.orig/drivers/char/Makefile	Fri Feb 25 11:51:32 2005
+++ linux-2.6.11-rc5/drivers/char/Makefile	Fri Feb 25 11:55:46 2005
@@ -80,6 +80,8 @@
 obj-$(CONFIG_NWBUTTON) += nwbutton.o
 obj-$(CONFIG_NWFLASH) += nwflash.o
 obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
+obj-$(CONFIG_AT91_SPI) += at91_spi.o
+obj-$(CONFIG_AT91_SPIDEV) += at91_spidev.o
 
 obj-$(CONFIG_WATCHDOG)	+= watchdog/
 obj-$(CONFIG_MWAVE) += mwave/
diff -urN linux-2.6.11-rc5.orig/drivers/char/at91_spi.c linux-2.6.11-rc5/drivers/char/at91_spi.c
--- linux-2.6.11-rc5.orig/drivers/char/at91_spi.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/char/at91_spi.c	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,275 @@
+/*
+ * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 (Thunder)
+ *
+ * (c) SAN People (Pty) Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <asm/semaphore.h>
+#include <linux/pci.h>
+#include <linux/sched.h>
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include <linux/at91_spi.h>
+
+#include <asm/arch/AT91RM9200_SPI.h>
+#include <asm/arch/pio.h>
+
+#undef DEBUG_SPI
+
+static struct spi_local spi_dev[NR_SPI_DEVICES];	/* state of the SPI devices */
+static int spi_enabled = 0;
+static struct semaphore spi_lock;			/* protect access to SPI bus */
+static int current_device = -1;				/* currently selected SPI device */
+
+DECLARE_COMPLETION(transfer_complete);
+
+/* SPI controller device */
+static AT91PS_SPI controller = (AT91PS_SPI) AT91C_VA_BASE_SPI;
+
+/* ......................................................................... */
+
+/*
+ * Access and enable the SPI bus.
+ * This MUST be called before any transfers are performed.
+ */
+void spi_access_bus(short device)
+{
+	/* Ensure that requested device is valid */
+	if ((device < 0) || (device >= NR_SPI_DEVICES))
+		panic("at91_spi: spi_access_bus called with invalid device");
+
+	if (spi_enabled == 0) {
+		AT91_SYS->PMC_PCER = 1 << AT91C_ID_SPI;	/* Enable Peripheral clock */
+		controller->SPI_CR = AT91C_SPI_SPIEN;	/* Enable SPI */
+#ifdef DEBUG_SPI
+		printk("SPI on\n");
+#endif
+	}
+	spi_enabled++;
+
+	/* Lock the SPI bus */
+	down(&spi_lock);
+	current_device = device;
+
+	/* Enable PIO */
+	if (!spi_dev[device].pio_enabled) {
+		switch (device) {
+			case 0: AT91_CfgPIO_SPI_CS0();  break;
+			case 1: AT91_CfgPIO_SPI_CS1();  break;
+			case 2: AT91_CfgPIO_SPI_CS2();  break;
+			case 3: AT91_CfgPIO_SPI_CS3();  break;
+		}
+		spi_dev[device].pio_enabled = 1;
+#ifdef DEBUG_SPI
+		printk("SPI CS%i enabled\n", device);
+#endif
+	}
+
+	/* Configure SPI bus for device */
+	controller->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | (spi_dev[device].pcs << 16);
+}
+
+/*
+ * Relinquish control of the SPI bus.
+ */
+void spi_release_bus(short device)
+{
+	if (device != current_device)
+		panic("at91_spi: spi_release called with invalid device");
+
+	/* Release the SPI bus */
+	current_device = -1;
+	up(&spi_lock);
+
+	spi_enabled--;
+	if (spi_enabled == 0) {
+		controller->SPI_CR = AT91C_SPI_SPIDIS;	/* Disable SPI */
+		AT91_SYS->PMC_PCER = 1 << AT91C_ID_SPI;	/* Disable Peripheral clock */
+#ifdef DEBUG_SPI
+		printk("SPI off\n");
+#endif
+	}
+}
+
+/*
+ * Perform a data transfer over the SPI bus
+ */
+int spi_transfer(struct spi_transfer_list* list)
+{
+	struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
+
+	if (!list)
+		panic("at91_spi: spi_transfer called with NULL transfer list");
+	if (current_device == -1)
+		panic("at91_spi: spi_transfer called without acquiring bus");
+
+#ifdef DEBUG_SPI
+	printk("SPI transfer start [%i]\n", list->nr_transfers);
+#endif
+
+	/* Store transfer list */
+	device->xfers = list;
+	list->curr = 0;
+
+	/* Assume there must be at least one transfer */
+	device->tx = pci_map_single(NULL, list->tx[0], list->txlen[0], PCI_DMA_TODEVICE);
+	device->rx = pci_map_single(NULL, list->rx[0], list->rxlen[0], PCI_DMA_FROMDEVICE);
+
+	/* Program PDC registers */
+	controller->SPI_TPR = device->tx;
+	controller->SPI_RPR = device->rx;
+	controller->SPI_TCR = list->txlen[0];
+	controller->SPI_RCR = list->rxlen[0];
+
+	/* Is there a second transfer? */
+	if (list->nr_transfers > 1) {
+		device->txnext = pci_map_single(NULL, list->tx[1], list->txlen[1], PCI_DMA_TODEVICE);
+		device->rxnext = pci_map_single(NULL, list->rx[1], list->rxlen[1], PCI_DMA_FROMDEVICE);
+
+		/* Program Next PDC registers */
+		controller->SPI_TNPR = device->txnext;
+		controller->SPI_RNPR = device->rxnext;
+		controller->SPI_TNCR = list->txlen[1];
+		controller->SPI_RNCR = list->rxlen[1];
+	}
+	else {
+		device->txnext = 0;
+		device->rxnext = 0;
+		controller->SPI_TNCR = 0;
+		controller->SPI_RNCR = 0;
+	}
+
+	// TODO: If we are doing consecutive transfers (at high speed, or
+	//   small buffers), then it might be worth modifying the 'Delay between
+	//   Consecutive Transfers' in the CSR registers.
+	//   This is an issue if we cannot chain the next buffer fast enough
+	//   in the interrupt handler.
+
+	/* Enable transmitter and receiver */
+	controller->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
+
+	controller->SPI_IER = AT91C_SPI_SPENDRX;	/* enable buffer complete interrupt */
+	wait_for_completion(&transfer_complete);
+
+#ifdef DEBUG_SPI
+	printk("SPI transfer end\n");
+#endif
+
+	return 0;
+}
+
+/* ......................................................................... */
+
+/*
+ * Handle interrupts from the SPI controller.
+ */
+static irqreturn_t spi_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ 	unsigned int status;
+	struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
+	struct spi_transfer_list *list = device->xfers;
+
+#ifdef DEBUG_SPI
+	printk("SPI interrupt %i\n", current_device);
+#endif
+
+	if (!list)
+		panic("at91_spi: spi_interrupt with a NULL transfer list");
+
+       	status = controller->SPI_SR & controller->SPI_IMR;	/* read status */
+
+	pci_unmap_single(NULL, device->tx, list->txlen[list->curr], PCI_DMA_TODEVICE);
+	pci_unmap_single(NULL, device->rx, list->rxlen[list->curr], PCI_DMA_FROMDEVICE);
+
+	device->tx = device->txnext;	/* move next transfer to current transfer */
+	device->rx = device->rxnext;
+
+	list->curr = list->curr + 1;
+	if (list->curr == list->nr_transfers) {		/* all transfers complete */
+		controller->SPI_IDR = AT91C_SPI_SPENDRX;	/* disable interrupt */
+
+		/* Disable transmitter and receiver */
+		controller->SPI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
+
+		device->xfers = NULL;
+		complete(&transfer_complete);
+	}
+	else if (list->curr+1 == list->nr_transfers) {	/* no more next transfers */
+		device->txnext = 0;
+		device->rxnext = 0;
+		controller->SPI_TNCR = 0;
+		controller->SPI_RNCR = 0;
+	}
+	else {
+		int i = (list->curr)+1;
+
+		device->txnext = pci_map_single(NULL, list->tx[i], list->txlen[i], PCI_DMA_TODEVICE);
+		device->rxnext = pci_map_single(NULL, list->rx[i], list->rxlen[i], PCI_DMA_FROMDEVICE);
+		controller->SPI_TNPR = device->txnext;
+		controller->SPI_RNPR = device->rxnext;
+		controller->SPI_TNCR = list->txlen[i];
+		controller->SPI_RNCR = list->rxlen[i];
+	}
+	return IRQ_HANDLED;
+}
+
+/* ......................................................................... */
+
+/*
+ * Initialize the SPI controller
+ */
+static int __init at91_spi_init(void)
+{
+	init_MUTEX(&spi_lock);
+
+	AT91_CfgPIO_SPI();
+
+	controller->SPI_CR = AT91C_SPI_SWRST;	/* software reset of SPI controller */
+
+	/* Set Chip Select registers to good defaults */
+	controller->SPI_CSR0 = AT91C_SPI_CPOL | AT91C_SPI_BITS_8 | (16 << 16) | (DEFAULT_SPI_BAUD << 8);
+	controller->SPI_CSR1 = AT91C_SPI_CPOL | AT91C_SPI_BITS_8 | (16 << 16) | (DEFAULT_SPI_BAUD << 8);
+	controller->SPI_CSR2 = AT91C_SPI_CPOL | AT91C_SPI_BITS_8 | (16 << 16) | (DEFAULT_SPI_BAUD << 8);
+	controller->SPI_CSR3 = AT91C_SPI_CPOL | AT91C_SPI_BITS_8 | (16 << 16) | (DEFAULT_SPI_BAUD << 8);
+
+	controller->SPI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
+
+	memset(&spi_dev, 0, sizeof(spi_dev));
+	spi_dev[0].pcs = 0xE;
+	spi_dev[1].pcs = 0xD;
+	spi_dev[2].pcs = 0xB;
+	spi_dev[3].pcs = 0x7;
+
+	if (request_irq(AT91C_ID_SPI, spi_interrupt, 0, "spi", NULL))
+		return -EBUSY;
+
+	controller->SPI_CR = AT91C_SPI_SPIEN;		/* Enable SPI */
+
+	return 0;
+}
+
+static void at91_spi_exit(void)
+{
+	controller->SPI_CR = AT91C_SPI_SPIDIS;		/* Disable SPI */
+
+	free_irq(AT91C_ID_SPI, 0);
+}
+
+
+EXPORT_SYMBOL(spi_access_bus);
+EXPORT_SYMBOL(spi_release_bus);
+EXPORT_SYMBOL(spi_transfer);
+
+module_init(at91_spi_init);
+module_exit(at91_spi_exit);
+
+MODULE_LICENSE("GPL")
+MODULE_AUTHOR("Andrew Victor")
+MODULE_DESCRIPTION("SPI driver for Atmel AT91RM9200")
diff -urN linux-2.6.11-rc5.orig/drivers/char/at91_spidev.c linux-2.6.11-rc5/drivers/char/at91_spidev.c
--- linux-2.6.11-rc5.orig/drivers/char/at91_spidev.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/char/at91_spidev.c	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,235 @@
+/*
+ * User-space interface to the SPI bus on Atmel AT91RM9200
+ *
+ * (c) SAN People (Pty) Ltd
+ *
+ * Based on SPI driver by Rick Bronson
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/highmem.h>
+#include <linux/pagemap.h>
+#include <linux/at91_spi.h>
+
+#ifdef CONFIG_DEVFS_FS
+#include <linux/devfs_fs_kernel.h>
+#endif
+
+
+#undef DEBUG_SPIDEV
+
+/* ......................................................................... */
+
+/*
+ * Read or Write to SPI bus.
+ */
+static ssize_t spidev_rd_wr(struct file *file, char *buf, size_t count, loff_t *offset)
+{
+	unsigned int spi_device = (unsigned int) file->private_data;
+
+	struct mm_struct * mm;
+	struct page ** maplist;
+	struct spi_transfer_list* list;
+	int    pgcount;
+	
+	unsigned int ofs, pagelen;
+	int res, i, err;
+
+	if (!count) {
+		return 0;
+	}
+	
+	list = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
+	if (!list) {
+		return -ENOMEM;
+	}
+
+	mm = current->mm; 
+	
+	pgcount = ((unsigned long)buf+count+PAGE_SIZE-1)/PAGE_SIZE - (unsigned long)buf/PAGE_SIZE;
+
+	if (pgcount >= MAX_SPI_TRANSFERS) {
+		kfree(list);
+		return -EFBIG;
+	}
+
+	maplist = kmalloc (pgcount * sizeof (struct page *), GFP_KERNEL);	
+
+	if (!maplist) {
+		kfree(list);
+		return -ENOMEM;	
+	}	
+	down_read(&mm->mmap_sem);
+	err= get_user_pages(current, mm, (unsigned long)buf, pgcount, 1, 0, maplist, NULL);	
+	up_read(&mm->mmap_sem);
+        
+	if (err < 0) {
+		kfree(list);
+		kfree(maplist);
+		return err;
+	}
+        pgcount = err;
+
+#ifdef DEBUG_SPIDEV
+	printk("spidev_rd_rw: %i %i\n", count, pgcount);
+#endif
+
+	/* Set default return value = transfer length */
+	res = count;
+
+	/*
+	 * At this point, the virtual area buf[0] .. buf[count-1] will have
+	 * corresponding pages mapped in the physical memory and locked until
+	 * we unmap the kiobuf.  The pages cannot be swapped out or moved
+	 * around.
+	 */
+	ofs = (unsigned long) buf & (PAGE_SIZE -1);
+	pagelen = PAGE_SIZE - ofs;
+	if (count < pagelen)
+		pagelen = count;
+
+	for (i = 0; i < pgcount; i++) {
+		flush_dcache_page(maplist[i]);
+		
+		list->tx[i] = list->rx[i] = page_address(maplist[i]) + ofs;
+		list->txlen[i] = list->rxlen[i] = pagelen;
+
+#ifdef DEBUG_SPIDEV
+		printk("  %i: %x  (%i)\n", i, list->tx[i], list->txlen[i]);
+#endif
+
+		ofs = 0;	/* all subsequent transfers start at beginning of a page */
+		count = count - pagelen;
+		pagelen = (count < PAGE_SIZE) ? count : PAGE_SIZE;
+	}
+	list->nr_transfers = pgcount;
+
+	/* Perform transfer on SPI bus */
+	spi_access_bus(spi_device);
+	spi_transfer(list);
+	spi_release_bus(spi_device);
+
+	while (pgcount--) {
+		page_cache_release (maplist[pgcount]);
+	}
+
+	kfree(maplist);
+	kfree(list);
+
+	return res;
+}
+
+static int spidev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+	int spi_device = MINOR(inode->i_rdev);
+
+	if (spi_device >= NR_SPI_DEVICES)
+		return -ENODEV;
+
+	// TODO: This interface can be used to configure the SPI bus.
+	// Configurable options could include: Speed, Clock Polarity, Clock Phase
+
+	switch(cmd) {
+		default:
+			return -ENOIOCTLCMD;
+	}
+}
+
+/*
+ * Open the SPI device
+ */
+static int spidev_open(struct inode *inode, struct file *file)
+{
+	unsigned int spi_device = MINOR(inode->i_rdev);
+
+	if (spi_device >= NR_SPI_DEVICES)
+		return -ENODEV;
+
+	/*
+	 * 'private_data' is actually a pointer, but we overload it with the
+	 * value we want to store.
+	 */
+	file->private_data = (void *)spi_device;
+
+	return 0;
+}
+
+/*
+ * Close the SPI device
+ */
+static int spidev_close(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+/* ......................................................................... */
+
+static struct file_operations spidev_fops = {
+	owner:		THIS_MODULE,
+	llseek:		no_llseek,
+	read:		spidev_rd_wr,
+	write:		(int (*) (struct file *file, const char *buf, size_t count, loff_t *offset))spidev_rd_wr,
+	ioctl:		spidev_ioctl,
+	open:		spidev_open,
+	release:	spidev_close,
+};
+
+/*
+ * Install the SPI /dev interface driver
+ */
+static int __init at91_spidev_init(void)
+{
+#ifdef CONFIG_DEVFS_FS
+	int i;
+#endif	
+	
+	if (register_chrdev(SPI_MAJOR, "spi", &spidev_fops)) {
+		printk(KERN_ERR "at91_spidev: Unable to get major %d for SPI bus\n", SPI_MAJOR);
+		return -EIO;
+	}
+
+#ifdef CONFIG_DEVFS_FS
+	devfs_mk_dir("spi");
+	for (i = 0; i < NR_SPI_DEVICES; i++) {
+		devfs_mk_cdev(MKDEV(SPI_MAJOR, i), S_IFCHR | S_IRUSR | S_IWUSR, "spi/%d",i);
+	}
+#endif	
+	printk(KERN_INFO "AT91 SPI driver loaded\n");
+
+	return 0;
+}
+
+/*
+ * Remove the SPI /dev interface driver
+ */
+static void __exit at91_spidev_exit(void)
+{
+#ifdef CONFIG_DEVFS_FS
+	int i;
+	for (i = 0; i < NR_SPI_DEVICES; i++) {
+		devfs_remove("spi/%d", i);
+	}
+	
+       	devfs_remove("spi");
+#endif	
+	
+	if (unregister_chrdev(SPI_MAJOR, "spi")) {
+		printk(KERN_ERR "at91_spidev: Unable to release major %d for SPI bus\n", SPI_MAJOR);
+		return;
+	}
+}
+
+module_init(at91_spidev_init);
+module_exit(at91_spidev_exit);
+
+MODULE_LICENSE("GPL")
+MODULE_AUTHOR("Andrew Victor")
+MODULE_DESCRIPTION("SPI /dev interface for Atmel AT91RM9200")
diff -urN linux-2.6.11-rc5.orig/drivers/char/watchdog/Kconfig linux-2.6.11-rc5/drivers/char/watchdog/Kconfig
--- linux-2.6.11-rc5.orig/drivers/char/watchdog/Kconfig	Fri Feb 25 11:51:33 2005
+++ linux-2.6.11-rc5/drivers/char/watchdog/Kconfig	Fri Feb 25 11:55:46 2005
@@ -139,6 +139,14 @@
 	  To compile this driver as a module, choose M here: the
 	  module will be called sa1100_wdt.
 
+config AT91_WATCHDOG
+	tristate "AT91RM9200 watchdog"
+	depends on WATCHDOG && ARCH_AT91RM9200
+	help
+	  Watchdog timer embedded into AT91RM9200 chips. This will reboot your
+	  system when the timeout is reached.
+	  
+
 # X86 (i386 + ia64 + x86_64) Architecture
 
 config ACQUIRE_WDT
diff -urN linux-2.6.11-rc5.orig/drivers/char/watchdog/Makefile linux-2.6.11-rc5/drivers/char/watchdog/Makefile
--- linux-2.6.11-rc5.orig/drivers/char/watchdog/Makefile	Fri Feb 25 11:50:32 2005
+++ linux-2.6.11-rc5/drivers/char/watchdog/Makefile	Fri Feb 25 11:55:46 2005
@@ -39,3 +39,4 @@
 obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
 obj-$(CONFIG_IXP2000_WATCHDOG) += ixp2000_wdt.o
 obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o
+obj-$(CONFIG_AT91_WATCHDOG) += at91_wdt.o
diff -urN linux-2.6.11-rc5.orig/drivers/char/watchdog/at91_wdt.c linux-2.6.11-rc5/drivers/char/watchdog/at91_wdt.c
--- linux-2.6.11-rc5.orig/drivers/char/watchdog/at91_wdt.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/char/watchdog/at91_wdt.c	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,185 @@
+/*
+ * Watchdog driver for Atmel AT91RM9200 (Thunder)
+ *
+ * (c) SAN People (Pty) Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/config.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <asm/bitops.h> 
+#include <asm/uaccess.h>
+#include <linux/init.h>
+
+#define WDT_DEFAULT_TIME 5	/* 5 seconds */
+#define WDT_MAX_TIME 256	/* 256 seconds */
+
+static int at91wdt_time = WDT_DEFAULT_TIME;
+static unsigned long at91wdt_busy;
+
+/* ......................................................................... */
+
+/*
+ * Disable the watchdog.
+ */
+static void at91_wdt_stop(void)
+{
+	AT91_SYS->ST_WDMR = AT91C_ST_EXTEN;
+}
+
+/*
+ * Enable and reset the watchdog.
+ */
+static void at91_wdt_start(void)
+{
+	AT91_SYS->ST_WDMR = AT91C_ST_EXTEN | AT91C_ST_RSTEN | (((65536 * at91wdt_time) >> 8) & AT91C_ST_WDV);
+	AT91_SYS->ST_CR = AT91C_ST_WDRST;
+}
+
+/* ......................................................................... */
+
+/*
+ * Watchdog device is opened, and watchdog starts running.
+ */
+static int at91_wdt_open(struct inode *inode, struct file *file)
+{
+	if (test_and_set_bit(1, &at91wdt_busy))
+		return -EBUSY;
+
+	/*
+	 * All counting occurs at SLOW_CLOCK / 128 = 0.256 Hz
+	 *
+	 * Since WDV is a 16-bit counter, the maximum period is
+	 * 65536 / 0.256 = 256 seconds.
+	 */
+
+	at91_wdt_start();
+	return 0;
+}
+
+/*
+ * Close the watchdog device.
+ * If CONFIG_WATCHDOG_NOWAYOUT is NOT defined then the watchdog is also
+ *  disabled.
+ */
+static int at91_wdt_close(struct inode *inode, struct file *file)
+{
+#ifndef CONFIG_WATCHDOG_NOWAYOUT
+	/* Disable the watchdog when file is closed */
+	at91_wdt_stop();
+#endif
+
+	at91wdt_busy = 0;
+	return 0;
+}
+
+/*
+ * Handle commands from user-space.
+ */
+static int at91_wdt_ioctl(struct inode *inode, struct file *file,
+		unsigned int cmd, unsigned long arg)
+{
+	unsigned int new_value;
+	static struct watchdog_info info = {
+		identity: "at91 watchdog",
+		options:  WDIOF_SETTIMEOUT,
+	};
+
+	switch(cmd) {
+		case WDIOC_KEEPALIVE:
+			AT91_SYS->ST_CR = AT91C_ST_WDRST;	/* Pat the watchdog */
+			return 0;
+
+		case WDIOC_GETSUPPORT:
+			return copy_to_user((struct watchdog_info *)arg, &info, sizeof(info));
+
+		case WDIOC_SETTIMEOUT:
+			if (get_user(new_value, (int *)arg))
+				return -EFAULT;
+			if ((new_value <= 0) || (new_value > WDT_MAX_TIME))
+				return -EINVAL;
+
+			/* Restart watchdog with new time */
+			at91wdt_time = new_value;
+			at91_wdt_start();
+
+			/* Return current value */
+			return put_user(at91wdt_time, (int *)arg);
+
+		case WDIOC_GETTIMEOUT:
+			return put_user(at91wdt_time, (int *)arg);
+
+		case WDIOC_GETSTATUS:
+			return put_user(0, (int *)arg);
+
+		case WDIOC_SETOPTIONS:
+			if (get_user(new_value, (int *)arg))
+				return -EFAULT;
+			if (new_value & WDIOS_DISABLECARD)
+				at91_wdt_stop();
+			if (new_value & WDIOS_ENABLECARD)
+				at91_wdt_start();
+			return 0;
+
+		default:
+			return -ENOIOCTLCMD;
+	}
+}
+
+/*
+ * Pat the watchdog whenever device is written to.
+ */
+static ssize_t at91_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos)
+{
+	AT91_SYS->ST_CR = AT91C_ST_WDRST;	/* Pat the watchdog */
+	return len;
+}
+
+/* ......................................................................... */
+
+static struct file_operations at91wdt_fops =
+{
+	.owner		= THIS_MODULE,
+	.ioctl		= at91_wdt_ioctl,
+	.open		= at91_wdt_open,
+	.release	= at91_wdt_close,
+	.write		= at91_wdt_write,
+};
+
+static struct miscdevice at91wdt_miscdev =
+{
+	.minor		= WATCHDOG_MINOR,
+	.name		= "watchdog",
+	.fops		= &at91wdt_fops,
+};
+
+static int __init at91_wdt_init(void)
+{
+	int res;
+
+	res = misc_register(&at91wdt_miscdev);
+	if (res)
+		return res;
+
+	printk("AT91 Watchdog Timer enabled (%d seconds)\n", WDT_DEFAULT_TIME);
+	return 0;
+}
+
+static void __exit at91_wdt_exit(void)
+{
+	misc_deregister(&at91wdt_miscdev);
+}
+
+module_init(at91_wdt_init);
+module_exit(at91_wdt_exit);
+
+MODULE_LICENSE("GPL")
+MODULE_AUTHOR("Andrew Victor")
+MODULE_DESCRIPTION("Watchdog driver for Atmel AT91RM9200")
diff -urN linux-2.6.11-rc5.orig/drivers/i2c/busses/Kconfig linux-2.6.11-rc5/drivers/i2c/busses/Kconfig
--- linux-2.6.11-rc5.orig/drivers/i2c/busses/Kconfig	Fri Feb 25 11:51:33 2005
+++ linux-2.6.11-rc5/drivers/i2c/busses/Kconfig	Fri Feb 25 11:55:46 2005
@@ -84,6 +84,13 @@
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-au1550.
 
+config I2C_AT91
+	tristate "Atmel AT91RM9200 I2C Two-Wire interface (TWI)"
+	depends on I2C && ARCH_AT91RM9200
+	help
+	  This supports the use of the I2C interface on the AT91RM9200
+	  processor.
+
 config I2C_ELEKTOR
 	tristate "Elektor ISA card"
 	depends on I2C && ISA && BROKEN_ON_SMP
diff -urN linux-2.6.11-rc5.orig/drivers/i2c/busses/Makefile linux-2.6.11-rc5/drivers/i2c/busses/Makefile
--- linux-2.6.11-rc5.orig/drivers/i2c/busses/Makefile	Fri Feb 25 11:51:33 2005
+++ linux-2.6.11-rc5/drivers/i2c/busses/Makefile	Fri Feb 25 11:55:46 2005
@@ -40,6 +40,7 @@
 obj-$(CONFIG_I2C_VOODOO3)	+= i2c-voodoo3.o
 obj-$(CONFIG_SCx200_ACB)	+= scx200_acb.o
 obj-$(CONFIG_SCx200_I2C)	+= scx200_i2c.o
+obj-$(CONFIG_I2C_AT91)		+= at91_i2c.o
 
 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
 EXTRA_CFLAGS += -DDEBUG
diff -urN linux-2.6.11-rc5.orig/drivers/i2c/busses/at91_i2c.c linux-2.6.11-rc5/drivers/i2c/busses/at91_i2c.c
--- linux-2.6.11-rc5.orig/drivers/i2c/busses/at91_i2c.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/i2c/busses/at91_i2c.c	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,234 @@
+/*
+    i2c Support for Atmel's AT91RM9200 Two-Wire Interface
+
+    (c) Rick Bronson
+
+    Borrowed heavily from original work by:
+    Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+*/
+
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+
+#include <asm/arch/AT91RM9200_TWI.h>
+#include <asm/arch/pio.h>
+#include "at91_i2c.h"
+
+#define DBG(x...) do {\
+	if (debug > 0) \
+		printk(KERN_DEBUG "i2c:" x); \
+	} while(0)
+
+static int debug = 0;
+
+static struct at91_i2c_local *at91_i2c_device;
+
+/*
+ * Poll the i2c status register until the specified bit is set.
+ * Returns 0 if timed out (100 msec)
+ */
+static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
+	int loop_cntr = 10000;
+	do {
+		udelay(10);
+	} while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
+
+	return (loop_cntr > 0);
+}
+
+/*
+ * Generic i2c master transfer entrypoint
+ */
+static int at91_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
+{
+	struct at91_i2c_local *device = (struct at91_i2c_local *)(i2c_get_adapdata(adap));
+	AT91PS_TWI twi = (AT91PS_TWI) device->base_addr;
+
+	struct i2c_msg *pmsg;
+	int length;
+	unsigned char *buf;
+
+	/*
+	 * i2c_smbus_xfer_emulated() in drivers/i2c/i2c-core.c states:
+	 * "... In the case of writing, we need to use only one message;
+	 * when reading, we need two..."
+	 */
+
+	pmsg = msgs;		/* look at 1st message, it contains the address/command */
+	if (num >= 1 && num <= 2) {
+		DBG("xfer: doing %s %d bytes to 0x%02x - %d messages\n",
+		    msgs[num-1].flags & I2C_M_RD ? "read" : "write",
+		    pmsg->len, pmsg->buf[0], num);
+
+		/* Set the TWI Master Mode Register */
+		twi->TWI_MMR = (pmsg->addr << 16) /* | (pmsg->len << 8) */
+			| (msgs[num-1].flags & I2C_M_RD ? AT91C_TWI_MREAD : 0);
+
+		/* Set TWI Internal Address Register with first messages data field */
+		if (pmsg->len == 1)
+			twi->TWI_IADR = pmsg->buf[0];
+		else if (pmsg->len == 2)
+			twi->TWI_IADR = pmsg->buf[0] << 8 | pmsg->buf[1];
+		else			/* must be 3 */
+			twi->TWI_IADR =  pmsg->buf[0] << 16 | pmsg->buf[1] << 8 | pmsg->buf[2];
+
+		/* 1st message contains the address/command */
+		if (num > 1)
+			pmsg++;		/* go to real message */
+
+		length = pmsg->len;
+		buf = pmsg->buf;
+		if (length && buf) {	/* sanity check */
+			if (pmsg->flags & I2C_M_RD) {
+				twi->TWI_CR = AT91C_TWI_START;
+				while (length--) {
+					if (!length)
+						twi->TWI_CR = AT91C_TWI_STOP;
+					/* Wait until transfer is finished */
+					if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
+						printk(KERN_ERR "at91_i2c: timeout 1\n");
+						return 0;
+					}
+					*buf++ = twi->TWI_RHR;
+				}
+				if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
+					printk(KERN_ERR "at91_i2c: timeout 2\n");
+					return 0;
+				}
+			} else {
+				twi->TWI_CR = AT91C_TWI_START;
+				while (length--) {
+					twi->TWI_THR = *buf++;
+					if (!length)
+						twi->TWI_CR = AT91C_TWI_STOP;
+					if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
+						printk(KERN_ERR "at91_i2c: timeout 3\n");
+						return 0;
+					}
+				}
+				/* Wait until transfer is finished */
+				if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
+					printk(KERN_ERR "at91_i2c: timeout 4\n");
+					return 0;
+				}
+			}
+		}
+		DBG("transfer complete\n");
+		return num;
+	}
+	else {
+		printk(KERN_ERR "at91_i2c: unexpected number of messages: %d\n", num);
+		return 0;
+	}
+}
+
+/*
+ * Return list of supported functionality
+ */
+static u32 at91_func(struct i2c_adapter *adapter)
+{
+	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE
+		| I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA
+		| I2C_FUNC_SMBUS_BLOCK_DATA;
+}
+
+/* For now, we only handle combined mode (smbus) */
+static struct i2c_algorithm at91_algorithm = {
+	name:"at91 i2c",
+	id:I2C_ALGO_SMBUS,
+	master_xfer:at91_xfer,
+	functionality:at91_func,
+};
+
+/*
+ * Main initialization routine
+ */
+static int __init i2c_at91_init(void)
+{
+	AT91PS_TWI twi = (AT91PS_TWI) AT91C_VA_BASE_TWI;
+	struct at91_i2c_local *device;
+	int rc;
+
+	AT91_CfgPIO_TWI();
+	AT91_SYS->PMC_PCER = 1 << AT91C_ID_TWI;		/* enable peripheral clock */
+
+	twi->TWI_IDR = 0x3ff;				/* Disable all interrupts */
+	twi->TWI_CR = AT91C_TWI_SWRST;			/* Reset peripheral */
+	twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;	/* Set Master mode */
+
+	/* Here, CKDIV = 1 and CHDIV=CLDIV  ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
+	twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
+
+	device = (struct at91_i2c_local *) kmalloc(sizeof(struct at91_i2c_local), GFP_KERNEL);
+	if (device == NULL) {
+		printk(KERN_ERR "at91_i2c: can't allocate inteface!\n");
+		return -ENOMEM;
+	}
+	memset(device, 0, sizeof(struct at91_i2c_local));
+	at91_i2c_device = device;
+	i2c_set_adapdata(&(device->adapter), device);
+
+	sprintf(device->adapter.name, "AT91RM9200");
+	device->adapter.id = I2C_ALGO_SMBUS;
+	device->adapter.algo = &at91_algorithm;
+	device->adapter.algo_data = NULL;
+	device->adapter.client_register = NULL;
+	device->adapter.client_unregister = NULL;
+	device->base_addr = AT91C_VA_BASE_TWI;
+
+	rc = i2c_add_adapter(&device->adapter);
+	if (rc) {
+		printk(KERN_ERR "at91_i2c: Adapter %s registration failed\n", device->adapter.name);
+		kfree(device);
+	}
+	else
+		printk(KERN_INFO "Found AT91 i2c\n");
+	return rc;
+}
+
+/*
+ * Clean up routine
+ */
+static void __exit i2c_at91_cleanup(void)
+{
+	struct at91_i2c_local *device = at91_i2c_device;
+	int rc;
+
+	rc = i2c_del_adapter(&device->adapter);
+	kfree(device);
+	
+	AT91_SYS->PMC_PCDR = 1 << AT91C_ID_TWI;		/* disable peripheral clock */
+
+	/* We aren't that prepared to deal with this... */
+	if (rc)
+		printk(KERN_ERR "at91_i2c: i2c_del_adapter failed (%i), that's bad!\n", rc);
+}
+
+module_init(i2c_at91_init);
+module_exit(i2c_at91_cleanup);
+
+MODULE_AUTHOR("Rick Bronson");
+MODULE_DESCRIPTION("I2C driver for Atmel AT91RM9200");
+MODULE_LICENSE("GPL");
diff -urN linux-2.6.11-rc5.orig/drivers/i2c/busses/at91_i2c.h linux-2.6.11-rc5/drivers/i2c/busses/at91_i2c.h
--- linux-2.6.11-rc5.orig/drivers/i2c/busses/at91_i2c.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/i2c/busses/at91_i2c.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,43 @@
+/*
+    i2c Support for Atmel's AT91RM9200 Two-Wire Interface
+
+    (c) Rick Bronson
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef AT91_I2C_H
+#define AT91_I2C_H
+
+#define AT91C_TWI_CLOCK		100000
+#define AT91C_TWI_SCLOCK	(10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK)
+#define AT91C_TWI_CKDIV1	(2 << 16)	/* TWI clock divider.  NOTE: see Errata #22 */
+
+#if (AT91C_TWI_SCLOCK % 10) >= 5
+#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5)
+#else
+#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 6)
+#endif
+#define AT91C_TWI_CLDIV3 ((AT91C_TWI_CLDIV2 + (4 - AT91C_TWI_CLDIV2 % 4)) >> 2)
+
+#define AT91C_EEPROM_I2C_ADDRESS        (0x50 << 16)
+
+/* Physical interface */
+struct at91_i2c_local {
+	struct i2c_adapter adapter;
+	unsigned long base_addr;
+};
+
+#endif
diff -urN linux-2.6.11-rc5.orig/drivers/mmc/Kconfig linux-2.6.11-rc5/drivers/mmc/Kconfig
--- linux-2.6.11-rc5.orig/drivers/mmc/Kconfig	Fri Feb 25 11:51:37 2005
+++ linux-2.6.11-rc5/drivers/mmc/Kconfig	Fri Feb 25 12:47:20 2005
@@ -60,4 +60,12 @@
 
 	  If unsure, say N.
 
+config MMC_AT91RM9200
+	tristate "AT91RM9200 SD/MMC Card Interface support"
+	depends on ARCH_AT91RM9200 && MMC
+	help
+	  This selects the AT91RM9200 MCI controller.
+
+	  If unsure, say N.
+	
 endmenu
diff -urN linux-2.6.11-rc5.orig/drivers/mmc/Makefile linux-2.6.11-rc5/drivers/mmc/Makefile
--- linux-2.6.11-rc5.orig/drivers/mmc/Makefile	Fri Feb 25 11:50:37 2005
+++ linux-2.6.11-rc5/drivers/mmc/Makefile	Fri Feb 25 12:47:20 2005
@@ -18,5 +18,6 @@
 obj-$(CONFIG_MMC_ARMMMCI)	+= mmci.o
 obj-$(CONFIG_MMC_PXA)		+= pxamci.o
 obj-$(CONFIG_MMC_WBSD)		+= wbsd.o
+obj-$(CONFIG_MMC_AT91RM9200)	+= at91rm9200_mci.o
 
 mmc_core-y := mmc.o mmc_queue.o mmc_sysfs.o
diff -urN linux-2.6.11-rc5.orig/drivers/mmc/at91rm9200_mci.c linux-2.6.11-rc5/drivers/mmc/at91rm9200_mci.c
--- linux-2.6.11-rc5.orig/drivers/mmc/at91rm9200_mci.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/mmc/at91rm9200_mci.c	Fri Feb 25 13:22:53 2005
@@ -0,0 +1,932 @@
+/*
+ *  linux/drivers/mmc/at91rm9200_mci.c - ATMEL AT91RM9200 MCI Driver
+ *
+ *  Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+   This is the AT91RM9200 MCI driver that has been tested with MMC cards only.
+   The CCAT91SBC001 board does not support SD cards.
+
+   The two entry points are at91rm9200_mci_request and at91rm9200_mci_set_ios.
+
+   SET IOS
+     This configures the device to put it into the correct mode and clock speed
+     required.
+
+   MCI REQUEST
+     MCI request processes the commands sent in the mmc_request structure. This
+     can consist of a processing command and a stop command in the case of
+     multiple block transfers.
+
+     There are three main types of request, commands, reads and writes.
+
+     Commands are straight forward. The command is submitted to the controller and
+     the request function returns. When the controller generates an interrupt to indicate
+     the command is finished, the response to the command are read and the mmc_request_done
+     function called to end the request.
+
+     Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
+     controller to manage the transfers.
+
+     A read is done from the controller directly to the scatterlist passed in from the request.
+     Due to a bug in the controller, when a read is completed, all the words are byte
+     swapped in the scatterlist buffers.
+
+     The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
+
+     A write is slightly different in that the bytes to write are read from the scatterlist
+     into a dma memory buffer (this is in case the source buffer should be read only). The
+     entire write buffer is then done from this single dma memory buffer.
+
+     The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/protocol.h>
+#include <linux/pci.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/mmc.h>
+#include <asm/arch/pio.h>
+#include <asm/arch/AT91RM9200_MCI.h>
+
+#define BYTE_SWAP4(x) \
+  (((x & 0xFF000000) >> 24) | \
+   ((x & 0x00FF0000) >> 8) | \
+   ((x & 0x0000FF00) << 8)  | \
+   ((x & 0x000000FF) << 24))
+
+#define DRIVER_NAME "at91rm9200_mci"
+
+#ifdef CONFIG_MMC_DEBUG
+#define DBG(fmt...)	\
+	printk(fmt)
+#else
+#define DBG(fmt...)	do { } while (0)
+#endif
+
+/* MCI Controller device */
+static AT91PS_MCI controller = (AT91PS_MCI)AT91C_VA_BASE_MCI;
+
+/* The command register values for each command */
+static const u32 commands[64] = {
+	/* Class 1  (0) */
+	MMC_GO_IDLE_STATE,
+	MMC_SEND_OP_COND	| AT91C_MCI_RSPTYP_48,
+	MMC_ALL_SEND_CID	| AT91C_MCI_RSPTYP_136,
+	MMC_SET_RELATIVE_ADDR	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT,
+	MMC_SET_DSR		| AT91C_MCI_MAXLAT,
+	0,
+	0,
+	MMC_SELECT_CARD		| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT,
+	0,
+	MMC_SEND_CSD		| AT91C_MCI_RSPTYP_136	| AT91C_MCI_MAXLAT,
+	MMC_SEND_CID		| AT91C_MCI_RSPTYP_136	| AT91C_MCI_MAXLAT,
+	MMC_READ_DAT_UNTIL_STOP	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT | AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_STREAM,
+	MMC_STOP_TRANSMISSION	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT | AT91C_MCI_TRCMD_STOP,
+	MMC_SEND_STATUS		| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT,
+	0,
+	MMC_GO_INACTIVE_STATE,
+
+	/* Class 2 (16) */
+	MMC_SET_BLOCKLEN	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT,
+	MMC_READ_SINGLE_BLOCK	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT | AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_BLOCK,
+	MMC_READ_MULTIPLE_BLOCK	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT | AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_MULTIPLE,
+	0,
+
+	/* Class 3 (20) */
+	MMC_WRITE_DAT_UNTIL_STOP| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT                   | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_STREAM,
+	0,
+	0,
+
+	/* Class 4 (23) */
+	MMC_SET_BLOCK_COUNT	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT,
+	MMC_WRITE_BLOCK		| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT                   | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_BLOCK,
+	MMC_WRITE_MULTIPLE_BLOCK| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT                   | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_MULTIPLE,
+	MMC_PROGRAM_CID		| AT91C_MCI_RSPTYP_48	| AT91C_MCI_MAXLAT,
+	MMC_PROGRAM_CSD		| AT91C_MCI_RSPTYP_48,
+
+	/* Class 6 (28) */
+	MMC_SET_WRITE_PROT	| AT91C_MCI_RSPTYP_48,
+	MMC_CLR_WRITE_PROT	| AT91C_MCI_RSPTYP_48,
+	MMC_SEND_WRITE_PROT	| AT91C_MCI_RSPTYP_48,
+	0,
+
+	/* Class 5 (32) */
+	0,
+	0,
+	0,
+	MMC_ERASE_GROUP_START	| AT91C_MCI_RSPTYP_48,
+	MMC_ERASE_GROUP_END	| AT91C_MCI_RSPTYP_48,
+	MMC_ERASE		| AT91C_MCI_RSPTYP_48 	| AT91C_MCI_MAXLAT,
+	0,
+
+	/* Class 9 (39) */
+	MMC_FAST_IO		| AT91C_MCI_RSPTYP_48 	| AT91C_MCI_MAXLAT,
+	MMC_GO_IRQ_STATE	| AT91C_MCI_RSPTYP_48 	| AT91C_MCI_MAXLAT,
+	0,
+
+	/* Class 7 (42) */
+	MMC_LOCK_UNLOCK		| AT91C_MCI_RSPTYP_48 	| AT91C_MCI_MAXLAT,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+
+	/* Class 8 (55) */
+	MMC_APP_CMD		| AT91C_MCI_RSPTYP_48 	| AT91C_MCI_MAXLAT,
+	MMC_GEN_CMD		| AT91C_MCI_RSPTYP_48 	| AT91C_MCI_MAXLAT,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0
+};
+
+#define FL_SENT_COMMAND (1 << 0)
+#define FL_SENT_STOP (1 << 1)
+
+/* Low level type for this driver
+ */
+struct at91mci_host
+{
+	struct mmc_host* mmc;
+	struct mmc_command* cmd;
+	struct mmc_request* request;
+
+	/*
+	 * Flag indicating when the command has been sent. This is used to
+	 * work out whether or not to send the stop
+	 */
+	unsigned int flags;
+
+	/* DMA buffer used for transmitting */
+	unsigned int* buffer;
+	dma_addr_t physical_address;
+	unsigned int total_length;
+
+	/* Latest in the scatterlist that has been enabled for transfer, but not freed */
+	int in_use_index;
+
+	/* Latest in the scatterlist that has been enabled for transfer */
+	int transfer_index;
+};
+
+/*
+ * Copy from sg to a dma block - used for transfers
+ */
+static inline void at91mci_sg_to_dma(struct at91mci_host* host, struct mmc_data* data)
+{
+	unsigned int len, i, size;
+	unsigned* dmabuf = host->buffer;
+
+	size = host->total_length;
+
+	len = data->sg_len;
+
+	/*
+	 * Just loop through all entries. Size might not
+	 * be the entire list though so make sure that
+	 * we do not transfer too much.
+	 */
+	for (i = 0;i < len;i++)
+	{
+		struct scatterlist* sg;
+		int amount;
+		int index;
+		unsigned int* sgbuffer;
+
+		sg = &data->sg[i];
+
+		sgbuffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
+		amount = min(size, sg->length);
+		size -= amount;
+		amount /= 4;
+
+		for (index = 0; index < amount; index++) {
+			*dmabuf++ = BYTE_SWAP4(sgbuffer[index]);
+		}
+		kunmap_atomic(sg->page, KM_BIO_SRC_IRQ);
+
+		if (size == 0)
+			break;
+	}
+
+	/*
+	 * Check that we didn't get a request to transfer
+	 * more data than can fit into the SG list.
+	 */
+	BUG_ON(size != 0);
+}
+
+/*
+ * Prepare a dma read
+ */
+static void at91mci_pre_dma_read(struct at91mci_host* host)
+{
+	int i;
+	struct scatterlist* sg;
+	struct mmc_command* cmd;
+	struct mmc_data* data;
+
+	DBG("pre dma read\n");
+
+	cmd = host->cmd;
+	if (!cmd) {
+		DBG("no command\n");
+		return;
+	}
+
+	data = cmd->data;
+	if (!data) {
+		DBG("no data\n");
+		return;
+	}
+
+	for (i = 0; i < 2; i++) {
+		/* nothing left to transfer */
+		if (host->transfer_index >= data->sg_len) {
+			DBG("Nothing left to transfer (index = %d)\n", host->transfer_index);
+			break;
+		}
+
+		/* Check to see if this needs filling */
+		if (i == 0) {
+			if (controller->MCI_RCR != 0) {
+				DBG("Transfer active in current\n");
+				continue;
+			}
+		}
+		else {
+			if (controller->MCI_RNCR != 0) {
+				DBG("Transfer active in next\n");
+				continue;
+			}
+		}
+
+		/* Setup the next transfer */
+		DBG("Using transfer index %d\n", host->transfer_index);
+
+		sg = &data->sg[host->transfer_index++];
+		DBG("sg = %p\n", sg);
+
+		sg->dma_address =
+			dma_map_page(NULL, sg->page, sg->offset, sg->length, DMA_FROM_DEVICE);
+
+		DBG("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
+
+		if (i == 0) {
+			controller->MCI_RPR = sg->dma_address;
+			controller->MCI_RCR = sg->length / 4;
+		}
+		else {
+			controller->MCI_RNPR = sg->dma_address;
+			controller->MCI_RNCR = sg->length / 4;
+		}
+	}
+
+	DBG("pre dma read done\n");
+}
+
+/* Handle after a dma read
+ */
+static void at91mci_post_dma_read(struct at91mci_host* host)
+{
+	struct mmc_command* cmd;
+	struct mmc_data* data;
+
+	DBG("post dma read\n");
+
+	cmd = host->cmd;
+	if (!cmd) {
+		DBG("no command\n");
+		return;
+	}
+
+	data = cmd->data;
+	if (!data) {
+		DBG("no data\n");
+		return;
+	}
+
+	while (host->in_use_index < host->transfer_index) {
+		unsigned int* buffer;
+		int index;
+		int len;
+
+		struct scatterlist* sg;
+
+		DBG("finishing index %d\n", host->in_use_index);
+
+		sg = &data->sg[host->in_use_index++];
+
+		DBG("Unmapping page %08X\n", sg->dma_address);
+
+		dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE);
+
+		/* Swap the contents of the buffer */
+		buffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
+		DBG("buffer = %p, length = %d\n", buffer, sg->length);
+
+		data->bytes_xfered += sg->length;
+
+		len = sg->length / 4;
+
+		for (index = 0; index < len; index++) {
+			buffer[index] = BYTE_SWAP4(buffer[index]);
+		}
+		kunmap_atomic(sg->page, KM_BIO_SRC_IRQ);
+	}
+
+	/* Is there another transfer to trigger? */
+	if (host->transfer_index < data->sg_len) {
+		at91mci_pre_dma_read(host);
+	}
+	else {
+		controller->MCI_IER = AT91C_MCI_RXBUFF;
+		controller->MCI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
+	}
+
+	DBG("post dma read done\n");
+}
+
+/*
+ * Handle transmitted data
+ */
+static void at91rm9200_mci_handle_transmitted(struct at91mci_host* host)
+{
+	struct mmc_command* cmd;
+	struct mmc_data* data;
+
+	DBG("Handling the transmit\n");
+
+	/* Disable the transfer */
+	controller->MCI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
+
+	/* Now wait for cmd ready */
+	controller->MCI_IDR = AT91C_MCI_TXBUFE;
+	controller->MCI_IER = AT91C_MCI_NOTBUSY;
+
+	cmd = host->cmd;
+	if (!cmd) return;
+
+	data = cmd->data;
+	if (!data) return;
+
+	data->bytes_xfered = host->total_length;
+}
+
+/*
+ * Enable the controller
+ */
+static void at91rm9200_mci_enable(void)
+{
+	AT91_SYS->PMC_PCER = 1 << AT91C_ID_MCI;		/* Enable the peripheral clock */
+	controller->MCI_CR = AT91C_MCI_MCIEN;
+	controller->MCI_IDR = 0xFFFFFFFF;
+	controller->MCI_DTOR = AT91C_MCI_DTOMUL_1048576 | AT91C_MCI_DTOCYC;
+	controller->MCI_MR = 0x834A;
+	controller->MCI_SDCR = 0x0;
+}
+
+/*
+ * Disable the controller
+ */
+static void at91rm9200_mci_disable(void)
+{
+	controller->MCI_CR = AT91C_MCI_MCIDIS | 0x80;
+	AT91_SYS->PMC_PCDR = 1 << AT91C_ID_MCI;		/* Disable the peripheral clock */
+}
+
+/*
+ * Send a command
+ * return the interrupts to enable
+ */
+static unsigned int at91rm9200_mci_send_command(struct at91mci_host* host, struct mmc_command* cmd)
+{
+	unsigned int cmdr;
+	unsigned int block_length;
+	struct mmc_data* data = cmd->data;
+	struct mmc_host* mmc = host->mmc;
+
+	unsigned int blocks;
+	unsigned int ier = 0;
+
+	host->cmd = cmd;
+
+	/* Not sure if this is needed */
+#if 0
+	if ((controller->MCI_SR & AT91C_MCI_RTOE) && (cmd->opcode == 1)) {
+		DBG("Clearing timeout\n");
+		controller->MCI_ARGR = 0;
+		controller->MCI_CMDR = AT91C_MCI_OPDCMD;
+		while (!(controller->MCI_SR & AT91C_MCI_CMDRDY)) {
+			/* spin */
+			DBG("Clearing: SR = %08X\n", controller->MCI_SR);
+		}
+	}
+#endif
+
+	cmdr = commands[cmd->opcode];
+	if (data) {
+		block_length = 1 << data->blksz_bits;
+		blocks = data->blocks;
+	}
+	else {
+		block_length = 0;
+		blocks = 0;
+	}
+
+	if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) {
+		cmdr |= AT91C_MCI_OPDCMD;
+	}
+
+	/*
+	 * Set the arguments and send the command
+	 */
+	DBG("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
+		cmd->opcode, cmdr, cmd->arg, blocks, block_length, controller->MCI_MR);
+
+	if (!data) {
+		controller->MCI_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS);
+		controller->MCI_RPR  = 0;
+		controller->MCI_RCR  = 0;
+		controller->MCI_RNPR  = 0;
+		controller->MCI_RNCR  = 0;
+		controller->MCI_TPR  = 0;
+		controller->MCI_TCR  = 0;
+		controller->MCI_TNPR  = 0;
+		controller->MCI_TNCR  = 0;
+
+		controller->MCI_ARGR = cmd->arg;
+		controller->MCI_CMDR = cmdr;
+		return AT91C_MCI_CMDRDY;
+	}
+
+	controller->MCI_MR &= ~0xFFFF8000;	/* zero block length and PDC mode */
+	controller->MCI_MR |= (block_length << 16) | AT91C_MCI_PDCMODE;
+
+	/*
+	 * Disable the PDC controller
+	 */
+	controller->MCI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
+
+	if (cmdr & AT91C_MCI_TRCMD_START) {
+		data->bytes_xfered = 0;
+		host->transfer_index = 0;
+		host->in_use_index = 0;
+		if (cmdr & AT91C_MCI_TRDIR) {
+			/*
+			 * Handle a read
+			 */
+			host->buffer = NULL;
+			host->total_length = 0;
+
+			at91mci_pre_dma_read(host);
+			ier = AT91C_MCI_ENDRX /* | AT91C_MCI_RXBUFF */;
+		} else {
+			/*
+			 * Handle a write
+			 */
+			host->total_length = block_length * blocks;
+			host->buffer = dma_alloc_coherent(NULL,
+							  host->total_length,
+							  &host->physical_address, GFP_KERNEL);
+
+			at91mci_sg_to_dma(host, data);
+
+			DBG("Transmitting %d bytes\n", host->total_length);
+
+			controller->MCI_TPR = host->physical_address;
+			controller->MCI_TCR = host->total_length / 4;
+			ier = AT91C_MCI_TXBUFE;
+		}
+	}
+
+	/*
+	 * Send the command and then enable the PDC - not the other way round as
+	 * the data sheet says
+	 */
+
+	controller->MCI_ARGR = cmd->arg;
+	controller->MCI_CMDR = cmdr;
+
+	if (cmdr & AT91C_MCI_TRCMD_START) {
+		if (cmdr & AT91C_MCI_TRDIR) {
+			controller->MCI_PTCR = AT91C_PDC_RXTEN;
+		}
+		else {
+			controller->MCI_PTCR = AT91C_PDC_TXTEN;
+		}
+	}
+
+	return ier;
+}
+
+/*
+ * Wait for a command to complete
+ */
+static void at91mci_process_command(struct at91mci_host* host, struct mmc_command* cmd)
+{
+	unsigned int ier;
+
+	ier = at91rm9200_mci_send_command(host, cmd);
+
+	DBG("setting ier to %08X\n", ier);
+
+	/* Stop on errors or the required value */
+	controller->MCI_IER = 0xffff0000 | ier;
+}
+
+/*
+ * Process the next step in the request
+ */
+static void at91mci_process_next(struct at91mci_host* host)
+{
+	if (!(host->flags & FL_SENT_COMMAND)) {
+		host->flags |= FL_SENT_COMMAND;
+		at91mci_process_command(host, host->request->cmd);
+	}
+	else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
+		host->flags |= FL_SENT_STOP;
+		at91mci_process_command(host, host->request->stop);
+	}
+	else {
+		mmc_request_done(host->mmc, host->request);
+	}
+}
+
+/*
+ * Handle a command that has been completed
+ */
+static void at91mci_completed_command(struct at91mci_host* host)
+{
+	struct mmc_command* cmd = host->cmd;
+	unsigned int status;
+
+	controller->MCI_IDR = 0xffffffff;
+
+	cmd->resp[0] = controller->MCI_RSPR[0];
+	cmd->resp[1] = controller->MCI_RSPR[1];
+	cmd->resp[2] = controller->MCI_RSPR[2];
+	cmd->resp[3] = controller->MCI_RSPR[3];
+
+	if (host->buffer) {
+		dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address);
+		host->buffer = NULL;
+	}
+
+	status = controller->MCI_SR;
+
+	DBG("Status = %08X [%08X %08X %08X %08X]\n",
+		 status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+
+	if (status & (AT91C_MCI_RINDE | AT91C_MCI_RDIRE | AT91C_MCI_RCRCE |
+			AT91C_MCI_RENDE | AT91C_MCI_RTOE | AT91C_MCI_DCRCE |
+			AT91C_MCI_DTOE | AT91C_MCI_OVRE | AT91C_MCI_UNRE)) {
+		if (cmd->opcode == MMC_SEND_OP_COND) {
+			cmd->error = MMC_ERR_NONE;
+		}
+		else {
+			if (status & (AT91C_MCI_RTOE | AT91C_MCI_DTOE)) {
+				cmd->error = MMC_ERR_TIMEOUT;
+			}
+			else if (status & (AT91C_MCI_RCRCE | AT91C_MCI_DCRCE)) {
+				cmd->error = MMC_ERR_BADCRC;
+			}
+			else if (status & (AT91C_MCI_OVRE | AT91C_MCI_UNRE)) {
+				cmd->error = MMC_ERR_FIFO;
+			}
+			else {
+				cmd->error = MMC_ERR_FAILED;
+			}
+
+			DBG("Error detected and set to %d (cmd = %d, retries = %d)\n",
+				 cmd->error, cmd->opcode, cmd->retries);
+		}
+	}
+	else {
+		cmd->error = MMC_ERR_NONE;
+	}
+
+	at91mci_process_next(host);
+}
+
+/*
+ * Handle an MMC request
+ */
+static void at91rm9200_mci_request(struct mmc_host* mmc, struct mmc_request* mrq)
+{
+	struct at91mci_host* host = mmc_priv(mmc);
+	host->request = mrq;
+	host->flags = 0;
+
+	at91mci_process_next(host);
+}
+
+/*
+ * Set the IOS
+ */
+static void at91rm9200_mci_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
+{
+	int clkdiv;
+
+	DBG("Clock %uHz, busmode %u, powermode %u, Vdd %u\n",
+		ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
+
+	if (ios->clock == 0) {
+		/* Disable the MCI controller */
+		controller->MCI_CR = AT91C_MCI_MCIDIS;
+		clkdiv = 0;
+	}
+	else {
+		/* Enable the MCI controller */
+		controller->MCI_CR = AT91C_MCI_MCIEN;
+
+		clkdiv = ((AT91C_MASTER_CLOCK / ios->clock) / 2) - 1;
+
+		DBG("clkdiv = %d. mcck = %d\n", clkdiv,
+			AT91C_MASTER_CLOCK / (2 * (clkdiv + 1)));
+	}
+
+	/* Set the clock divider */
+	controller->MCI_MR = (controller->MCI_MR & ~0x000000FF) | clkdiv;
+}
+
+/*
+ * Handle an interrupt
+ */
+static irqreturn_t at91rm9200_mci_irq(int irq, void* devid, struct pt_regs* regs)
+{
+	struct at91mci_host* host = devid;
+	int completed = 0;
+
+	unsigned int int_status;
+
+	if (host == NULL) {
+		return IRQ_HANDLED;
+	}
+
+	int_status = controller->MCI_SR;
+	DBG("MCI irq: status = %08X, %08X, %08X\n", int_status, controller->MCI_IMR,
+		int_status & controller->MCI_IMR);
+
+	if ((int_status & controller->MCI_IMR) & 0xffff0000) {
+		completed = 1;
+	}
+	int_status &= controller->MCI_IMR;
+
+	if (int_status & AT91C_MCI_UNRE) {
+		DBG("Underrun error\n");
+	}
+
+	if (int_status & AT91C_MCI_OVRE) {
+		DBG("Overrun error\n");
+	}
+
+	if (int_status & AT91C_MCI_DTOE) {
+		DBG("Data timeout\n");
+	}
+
+	if (int_status & AT91C_MCI_DCRCE) {
+		DBG("CRC error in data\n");
+	}
+
+	if (int_status & AT91C_MCI_RTOE) {
+		DBG("Response timeout\n");
+	}
+
+	if (int_status & AT91C_MCI_RENDE) {
+		DBG("Response end bit error\n");
+	}
+
+	if (int_status & AT91C_MCI_RCRCE) {
+		DBG("Response CRC error\n");
+	}
+
+	if (int_status & AT91C_MCI_RINDE) {
+		DBG("Response index error\n");
+	}
+
+	if (int_status & AT91C_MCI_TXBUFE) {
+		DBG("TX buffer empty\n");
+		at91rm9200_mci_handle_transmitted(host);
+	}
+
+	if (int_status & AT91C_MCI_RXBUFF) {
+		DBG("RX buffer full\n");
+		controller->MCI_IER = AT91C_MCI_CMDRDY;
+	}
+
+	if (int_status & AT91C_MCI_ENDTX) {
+		DBG("Transmit has ended\n");
+	}
+
+	if (int_status & AT91C_MCI_ENDRX) {
+		DBG("Receive has ended\n");
+		at91mci_post_dma_read(host);
+	}
+
+	if (int_status & AT91C_MCI_NOTBUSY) {
+		DBG("Card is ready\n");
+		controller->MCI_IER = AT91C_MCI_CMDRDY;
+	}
+
+	if (int_status & AT91C_MCI_DTIP) {
+		DBG("Data transfer in progress\n");
+	}
+
+	if (int_status & AT91C_MCI_BLKE) {
+		DBG("Black transfer has ended\n");
+	}
+
+	if (int_status & AT91C_MCI_TXRDY) {
+		DBG("Ready to transmit\n");
+	}
+
+	if (int_status & AT91C_MCI_RXRDY) {
+		DBG("Ready to receive\n");
+	}
+
+	if (int_status & AT91C_MCI_CMDRDY) {
+		DBG("Command ready\n");
+		completed = 1;
+	}
+
+	controller->MCI_IDR = int_status;
+
+	if (completed) {
+		DBG("Completed command\n");
+		controller->MCI_IDR = 0xffffffff;
+		at91mci_completed_command(host);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static struct mmc_host_ops at91rm9200_mci_ops = {
+	.request	= at91rm9200_mci_request,
+	.set_ios	= at91rm9200_mci_set_ios,
+};
+
+/*
+ * Probe for the device
+ */
+static int at91rm9200_mci_probe(struct device* dev)
+{
+	struct mmc_host* mmc;
+	struct at91mci_host* host;
+	int ret;
+
+	DBG("Probe MCI devices\n");
+
+	mmc = mmc_alloc_host(sizeof(struct at91mci_host), dev);
+	if (!mmc) {
+		DBG("Failed to allocate mmc host\n");
+
+		ret = -ENOMEM;
+		return ret;
+	}
+
+	mmc->ops = &at91rm9200_mci_ops;
+	mmc->f_min = 375000;
+	mmc->f_max = 24000000;
+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+	host = mmc_priv(mmc);
+	host->mmc = mmc;
+	host->buffer = NULL;
+
+	/*
+	 * Allocate the interrupt
+	 */
+	ret = request_irq(AT91C_ID_MCI, at91rm9200_mci_irq, SA_SHIRQ, DRIVER_NAME, host);
+	if (ret) {
+		DBG("Failed to request MCI interrupt\n");
+		return ret;
+	}
+
+	dev_set_drvdata(dev, mmc);
+
+	/*
+	 * Add host to MMC layer
+	 */
+	mmc_add_host(mmc);
+
+	DBG(KERN_INFO "Added MCI driver\n");
+
+	return 0;
+}
+
+/*
+ * Remove a device
+ */
+static int at91rm9200_mci_remove(struct device* dev)
+{
+	struct mmc_host* mmc = dev_get_drvdata(dev);
+	struct at91mci_host* host;
+
+	if (!mmc) return -1;
+
+	host = mmc_priv(mmc);
+
+	free_irq(AT91C_ID_MCI, host);
+	mmc_free_host(mmc);
+
+	DBG("Removed\n");
+
+	return 0;
+}
+
+static void at91rm9200_mci_release(struct device* dev)
+{
+	DBG("Release device\n");
+}
+
+static struct platform_device at91rm9200_mci_device = {
+	.name		= DRIVER_NAME,
+	.id		= -1,
+	.dev		= {
+		.release = at91rm9200_mci_release,
+	},
+};
+
+static struct device_driver at91rm9200_mci_driver = {
+	.name		= DRIVER_NAME,
+	.bus		= &platform_bus_type,
+	.probe		= at91rm9200_mci_probe,
+	.remove		= at91rm9200_mci_remove,
+};
+
+/* Initialise the MCI controller
+ */
+static int __init at91rm9200_mci_init(void)
+{
+	int result;
+
+	AT91_CfgPIO_MCISlotA();
+
+	at91rm9200_mci_disable();
+	at91rm9200_mci_enable();
+
+	result = driver_register(&at91rm9200_mci_driver);
+	if (result < 0) {
+		printk(KERN_ERR "AT91 MCI: Failed to register driver\n");
+		return result;
+	}
+
+	result = platform_device_register(&at91rm9200_mci_device);
+	if (result < 0) {
+		printk(KERN_ERR "AT91 MCI: Failed to register device\n");
+		return result;
+	}
+
+	printk(KERN_INFO "AT91RM9200 MCI initialized\n");
+
+	return 0;
+}
+
+/*
+ * Release the controller
+ */
+static void __exit at91rm9200_mci_exit(void)
+{
+	at91rm9200_mci_disable();
+	platform_device_unregister(&at91rm9200_mci_device);
+	driver_unregister(&at91rm9200_mci_driver);
+
+	printk(KERN_INFO "AT91RM9200 MCI removed\n");
+}
+
+module_init(at91rm9200_mci_init);
+module_exit(at91rm9200_mci_exit);
+
+MODULE_DESCRIPTION("AT91RM9200 Multimedia Card Interface driver");
+MODULE_AUTHOR("Nick Randell");
+MODULE_LICENSE("GPL");
diff -urN linux-2.6.11-rc5.orig/drivers/mtd/devices/Kconfig linux-2.6.11-rc5/drivers/mtd/devices/Kconfig
--- linux-2.6.11-rc5.orig/drivers/mtd/devices/Kconfig	Fri Feb 25 11:51:37 2005
+++ linux-2.6.11-rc5/drivers/mtd/devices/Kconfig	Fri Feb 25 11:55:46 2005
@@ -255,5 +255,20 @@
 	  LinuxBIOS or if you need to recover a DiskOnChip Millennium on which
 	  you have managed to wipe the first block.
 
+config MTD_AT91_DATAFLASH
+	bool "AT91RM9200 DataFlash AT45DBxxx"
+	depends on MTD && ARCH_AT91RM9200 && AT91_SPI
+        help
+          This enables access to the DataFlash chip (AT45DBxxx) on the
+          AT91RM9200-DK board.
+          If you have such a board, say 'Y'.
+
+config MTD_AT91_DATAFLASH_CARD
+	bool "Enable DataFlash Card support"
+        depends on MTD && ARCH_AT91RM9200 && AT91_SPI && MTD_AT91_DATAFLASH
+        help
+          This enables support for DataFlash cards
+
+
 endmenu
 
diff -urN linux-2.6.11-rc5.orig/drivers/mtd/devices/Makefile linux-2.6.11-rc5/drivers/mtd/devices/Makefile
--- linux-2.6.11-rc5.orig/drivers/mtd/devices/Makefile	Fri Feb 25 11:51:37 2005
+++ linux-2.6.11-rc5/drivers/mtd/devices/Makefile	Fri Feb 25 11:55:46 2005
@@ -23,3 +23,4 @@
 obj-$(CONFIG_MTD_LART)		+= lart.o
 obj-$(CONFIG_MTD_BLKMTD)	+= blkmtd.o
 obj-$(CONFIG_MTD_BLOCK2MTD)	+= block2mtd.o
+obj-$(CONFIG_MTD_AT91_DATAFLASH)+= at91_dataflash.o
diff -urN linux-2.6.11-rc5.orig/drivers/mtd/devices/at91_dataflash.c linux-2.6.11-rc5/drivers/mtd/devices/at91_dataflash.c
--- linux-2.6.11-rc5.orig/drivers/mtd/devices/at91_dataflash.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/mtd/devices/at91_dataflash.c	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,572 @@
+/*
+ * Atmel DataFlash driver for Atmel AT91RM9200 (Thunder)
+ *
+ * (c) SAN People (Pty) Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/at91_spi.h>
+
+#include <asm/arch/AT91RM9200_SPI.h>
+#include <asm/arch/pio.h>
+
+#undef DEBUG_DATAFLASH
+
+#define DATAFLASH_MAX_DEVICES	4	/* max number of dataflash devices */
+#undef	DATAFLASH_ALWAYS_ADD_DEVICE	/* always add whole device when using partitions? */
+
+#define OP_READ_CONTINUOUS	0xE8
+#define OP_READ_PAGE		0xD2
+#define OP_READ_BUFFER1		0xD4
+#define OP_READ_BUFFER2		0xD6
+#define OP_READ_STATUS		0xD7
+
+#define OP_ERASE_PAGE		0x81
+#define OP_ERASE_BLOCK		0x50
+
+#define OP_TRANSFER_BUF1	0x53
+#define OP_TRANSFER_BUF2	0x55
+#define OP_COMPARE_BUF1		0x60
+#define OP_COMPARE_BUF2		0x61
+
+#define OP_PROGRAM_VIA_BUF1	0x82
+#define OP_PROGRAM_VIA_BUF2	0x85
+
+struct dataflash_local
+{
+	int spi;			/* SPI chip-select number */
+
+	unsigned int page_size;		/* number of bytes per page */
+	unsigned short page_offset;	/* page offset in flash address */
+};
+
+
+/* Detected DataFlash devices */
+static struct mtd_info* mtd_devices[DATAFLASH_MAX_DEVICES];
+static int nr_devices = 0;
+
+/* ......................................................................... */
+
+#ifdef CONFIG_MTD_PARTITIONS
+
+#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
+
+static struct mtd_partition static_partitions[] =
+{
+	{
+		name:		"bootloader",
+		offset:		0,
+		size:		128 * 1056,		/* 64 Kb */
+		offset:		MTDPART_OFS_NXTBLK,
+	},
+	{
+		name:		"kernel",
+		offset:		MTDPART_OFS_NXTBLK,
+		size:		7 * 112 * 1056,		/* 768 Kb */
+	},
+	{
+		name:		"etcfs",
+		offset:		MTDPART_OFS_NXTBLK,
+		size:		128 *1056,		/* 128 Kb */
+	},
+	{
+		name:		"rootfs",
+		offset:		MTDPART_OFS_NXTBLK,
+		size:		MTDPART_SIZ_FULL,
+	}
+};
+
+int parse_cmdline_partitions(struct mtd_info *master,
+		struct mtd_partition **pparts, const char *mtd_id);
+
+#endif
+
+/* ......................................................................... */
+
+/* Allocate a single SPI transfer descriptor.  We're assuming that if multiple
+   SPI transfers occur at the same time, spi_access_bus() will serialize them.
+   If this is not valid, then either (i) each dataflash 'priv' structure
+   needs it's own transfer descriptor, (ii) we lock this one, or (iii) use
+   another mechanism.   */
+static struct spi_transfer_list* spi_transfer_desc;
+
+/*
+ * Perform a SPI transfer to access the DataFlash device.
+ */
+static int do_spi_transfer(int nr, char* tx, int tx_len, char* rx, int rx_len,
+		char* txnext, int txnext_len, char* rxnext, int rxnext_len)
+{
+	struct spi_transfer_list* list = spi_transfer_desc;
+
+	list->tx[0] = tx;	list->txlen[0] = tx_len;
+	list->rx[0] = rx;	list->rxlen[0] = rx_len;
+
+	list->tx[1] = txnext; 	list->txlen[1] = txnext_len;
+	list->rx[1] = rxnext;	list->rxlen[1] = rxnext_len;
+
+	list->nr_transfers = nr;
+
+	return spi_transfer(list);
+}
+
+/* ......................................................................... */
+
+/*
+ * Poll the DataFlash device until it is READY.
+ */
+static void at91_dataflash_waitready(void)
+{
+	char* command = kmalloc(2, GFP_KERNEL);
+
+	if (!command)
+		return;
+
+	do {
+		command[0] = OP_READ_STATUS;
+		command[1] = 0;
+
+		do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
+	} while ((command[1] & 0x80) == 0);
+
+	kfree(command);
+}
+
+/*
+ * Return the status of the DataFlash device.
+ */
+static unsigned short at91_dataflash_status(void)
+{
+	unsigned short status;
+	char* command = kmalloc(2, GFP_KERNEL);
+
+	if (!command)
+		return 0;
+
+	command[0] = OP_READ_STATUS;
+	command[1] = 0;
+
+	do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
+	status = command[1];
+
+	kfree(command);
+	return status;
+}
+
+/* ......................................................................... */
+
+/*
+ * Erase blocks of flash.
+ */
+static int at91_dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+	struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
+	unsigned int pageaddr;
+	char* command;
+
+#ifdef DEBUG_DATAFLASH
+	printk("dataflash_erase: addr=%i len=%i\n", instr->addr, instr->len);
+#endif
+
+	/* Sanity checks */
+	if (instr->addr + instr->len > mtd->size)
+		return -EINVAL;
+	if ((instr->len % mtd->erasesize != 0) || (instr->len % priv->page_size != 0))
+		return -EINVAL;
+	if ((instr->addr % priv->page_size) != 0)
+		return -EINVAL;
+
+	command = kmalloc(4, GFP_KERNEL);
+	if (!command)
+		return -ENOMEM;
+
+	while (instr->len > 0) {
+		/* Calculate flash page address */
+		pageaddr = (instr->addr / priv->page_size) << priv->page_offset;
+
+		command[0] = OP_ERASE_PAGE;
+		command[1] = (pageaddr & 0x00FF0000) >> 16;
+		command[2] = (pageaddr & 0x0000FF00) >> 8;
+		command[3] = 0;
+#ifdef DEBUG_DATAFLASH
+		printk("ERASE: (%x) %x %x %x [%i]\n", command[0], command[1], command[2], command[3], pageaddr);
+#endif
+
+		/* Send command to SPI device */
+		spi_access_bus(priv->spi);
+		do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
+
+		at91_dataflash_waitready();		/* poll status until ready */
+		spi_release_bus(priv->spi);
+
+		instr->addr += priv->page_size;		/* next page */
+		instr->len -= priv->page_size;
+	}
+
+	kfree(command);
+
+	/* Inform MTD subsystem that erase is complete */
+	instr->state = MTD_ERASE_DONE;
+	if (instr->callback)
+		instr->callback(instr);
+
+	return 0;
+}
+
+/*
+ * Read from the DataFlash device.
+ *   from   : Start offset in flash device
+ *   len    : Amount to read
+ *   retlen : About of data actually read
+ *   buf    : Buffer containing the data
+ */
+static int at91_dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
+{
+	struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
+	unsigned int addr;
+	char* command;
+
+#ifdef DEBUG_DATAFLASH
+	printk("dataflash_read: %lli .. %lli\n", from, from+len);
+#endif
+
+	*retlen = 0;
+
+	/* Sanity checks */
+	if (!len)
+		return 0;
+	if (from + len > mtd->size)
+		return -EINVAL;
+
+	/* Calculate flash page/byte address */
+	addr = (((unsigned)from / priv->page_size) << priv->page_offset) + ((unsigned)from % priv->page_size);
+
+	command = kmalloc(8, GFP_KERNEL);
+	if (!command)
+		return -ENOMEM;
+
+	command[0] = OP_READ_CONTINUOUS;
+	command[1] = (addr & 0x00FF0000) >> 16;
+	command[2] = (addr & 0x0000FF00) >> 8;
+	command[3] = (addr & 0x000000FF);
+#ifdef DEBUG_DATAFLASH
+	printk("READ: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
+#endif
+
+	/* Send command to SPI device */
+	spi_access_bus(priv->spi);
+	do_spi_transfer(2, command, 8, command, 8, buf, len, buf, len);
+	spi_release_bus(priv->spi);
+
+	*retlen = len;
+	kfree(command);
+	return 0;
+}
+
+/*
+ * Write to the DataFlash device.
+ *   to     : Start offset in flash device
+ *   len    : Amount to write
+ *   retlen : Amount of data actually written
+ *   buf    : Buffer containing the data
+ */
+static int at91_dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
+{
+	struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
+	unsigned int pageaddr, addr, offset, writelen;
+	size_t remaining;
+	u_char *writebuf;
+	unsigned short status;
+	int res = 0;
+	char* command;
+	char* tmpbuf = NULL;
+
+#ifdef DEBUG_DATAFLASH
+	printk("dataflash_write: %lli .. %lli\n", to, to+len);
+#endif
+
+	*retlen = 0;
+
+	/* Sanity checks */
+	if (!len)
+		return 0;
+	if (to + len > mtd->size)
+		return -EINVAL;
+
+	command = kmalloc(4, GFP_KERNEL);
+	if (!command)
+		return -ENOMEM;
+
+	pageaddr = ((unsigned)to / priv->page_size);
+	offset = ((unsigned)to % priv->page_size);
+	if (offset + len > priv->page_size)
+		writelen = priv->page_size - offset;
+	else
+		writelen = len;
+	writebuf = (u_char *)buf;
+	remaining = len;
+
+	/* Allocate temporary buffer */
+	tmpbuf = kmalloc(priv->page_size, GFP_KERNEL);
+	if (!tmpbuf) {
+		kfree(command);
+		return -ENOMEM;
+	}
+
+	/* Gain access to the SPI bus */
+	spi_access_bus(priv->spi);
+
+	while (remaining > 0) {
+#ifdef DEBUG_DATAFLASH
+		printk("write @ %i:%i len=%i\n", pageaddr, offset, writelen);
+#endif
+
+		/* (1) Transfer to Buffer1 */
+		if (writelen != priv->page_size) {
+			addr = pageaddr << priv->page_offset;
+			command[0] = OP_TRANSFER_BUF1;
+			command[1] = (addr & 0x00FF0000) >> 16;
+			command[2] = (addr & 0x0000FF00) >> 8;
+			command[3] = 0;
+#ifdef DEBUG_DATAFLASH
+			printk("TRANSFER: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
+#endif
+			do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
+			at91_dataflash_waitready();
+		}
+
+		/* (2) Program via Buffer1 */
+		addr = (pageaddr << priv->page_offset) + offset;
+		command[0] = OP_PROGRAM_VIA_BUF1;
+		command[1] = (addr & 0x00FF0000) >> 16;
+		command[2] = (addr & 0x0000FF00) >> 8;
+		command[3] = (addr & 0x000000FF);
+#ifdef DEBUG_DATAFLASH
+		printk("PROGRAM: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
+#endif
+		do_spi_transfer(2, command, 4, command, 4, writebuf, writelen, tmpbuf, writelen);
+		at91_dataflash_waitready();
+
+		/* (3) Compare to Buffer1 */
+		addr = pageaddr << priv->page_offset;
+		command[0] = OP_COMPARE_BUF1;
+		command[1] = (addr & 0x00FF0000) >> 16;
+		command[2] = (addr & 0x0000FF00) >> 8;
+		command[3] = 0;
+#ifdef DEBUG_DATAFLASH
+		printk("COMPARE: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
+#endif
+		do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
+		at91_dataflash_waitready();
+
+		/* Get result of the compare operation */
+		status = at91_dataflash_status();
+		if ((status & 0x40) == 1) {
+			printk("at91_dataflash: Write error on page %i\n", pageaddr);
+			remaining = 0;
+			res = -EIO;
+		}
+
+		remaining = remaining - writelen;
+		pageaddr++;
+		offset = 0;
+		writebuf += writelen;
+		*retlen += writelen;
+
+		if (remaining > priv->page_size)
+			writelen = priv->page_size;
+		else
+			writelen = remaining;
+	}
+
+	/* Release SPI bus */
+	spi_release_bus(priv->spi);
+
+	kfree(tmpbuf);
+	kfree(command);
+	return res;
+}
+
+/* ......................................................................... */
+
+/*
+ * Initialize and register DataFlash device with MTD subsystem.
+ */
+static int add_dataflash(int channel, char *name, int IDsize, int nr_pages, int pagesize, int pageoffset)
+{
+	struct mtd_info *device;
+	struct dataflash_local *priv;
+#ifdef CONFIG_MTD_PARTITIONS
+	struct mtd_partition *mtd_parts = 0;
+	int mtd_parts_nr = 0;
+#endif
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+	char mtdID[14];
+#endif
+
+	if (nr_devices >= DATAFLASH_MAX_DEVICES) {
+		printk(KERN_ERR "at91_dataflash: Too many devices detected\n");
+		return 0;
+	}
+
+	device = (struct mtd_info *) kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
+	if (!device)
+		return -ENOMEM;
+	memset(device, 0, sizeof(struct mtd_info));
+
+	device->name = name;
+	device->size = nr_pages * pagesize;
+	device->erasesize = pagesize;
+//	device->module = THIS_MODULE;
+	device->type = MTD_NORFLASH;
+	device->flags = MTD_CAP_NORFLASH;
+	device->erase = at91_dataflash_erase;
+	device->read = at91_dataflash_read;
+	device->write = at91_dataflash_write;
+
+	priv = (struct dataflash_local *) kmalloc(sizeof(struct dataflash_local), GFP_KERNEL);
+	if (!priv) {
+		kfree(device);
+		return -ENOMEM;
+	}
+	memset(priv, 0, sizeof(struct dataflash_local));
+
+	priv->spi = channel;
+	priv->page_size = pagesize;
+	priv->page_offset = pageoffset;
+	device->priv = priv;
+
+	mtd_devices[nr_devices] = device;
+	nr_devices++;
+	printk("at91_dataflash: %s detected [spi%i] (%i bytes)\n", name, channel, device->size);
+
+#ifdef CONFIG_MTD_PARTITIONS
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+	sprintf(mtdID, "dataflash%i", nr_devices-1);
+	mtd_parts_nr = parse_cmdline_partitions(device, &mtd_parts, mtdID);
+#endif
+	if (mtd_parts_nr <= 0) {
+		mtd_parts = static_partitions;
+		mtd_parts_nr = NB_OF(static_partitions);
+	}
+
+	if (mtd_parts_nr > 0) {
+#ifdef DATAFLASH_ALWAYS_ADD_DEVICE
+		add_mtd_device(device);
+#endif
+		return add_mtd_partitions(device, mtd_parts, mtd_parts_nr);
+	}
+#endif
+	return add_mtd_device(device);		/* add whole device */
+}
+
+/*
+ * Detect and initialize DataFlash device connected to specified SPI channel.
+ *
+ *   Device            Density         ID code                 Nr Pages        Page Size       Page offset
+ *   AT45DB011B        1Mbit   (128K)  xx0011xx (0x0c)         512             264             9
+ *   AT45DB021B        2Mbit   (256K)  xx0101xx (0x14)         1025            264             9
+ *   AT45DB041B        4Mbit   (512K)  xx0111xx (0x1c)         2048            264             9
+ *   AT45DB081B        8Mbit   (1M)    xx1001xx (0x24)         4096            264             9
+ *   AT45DB0161B       16Mbit  (2M)    xx1011xx (0x2c)         4096            528             10
+ *   AT45DB0321B       32Mbit  (4M)    xx1101xx (0x34)         8192            528             10
+ *   AT45DB0642        64Mbit  (8M)    xx1111xx (0x3c)         8192            1056            11
+ *   AT45DB1282        128Mbit (16M)   xx0100xx (0x10)         16384           1056            11
+ */
+static int at91_dataflash_detect(int channel)
+{
+	int res = 0;
+	unsigned short status;
+
+	spi_access_bus(channel);
+	status = at91_dataflash_status();
+	if (status != 0xff) {			/* no dataflash device there */
+		switch (status & 0x3c) {
+			case 0x0c:	/* 0 0 1 1 */
+				res = add_dataflash(channel, "Atmel AT45DB011B", SZ_128K, 512, 264, 9);
+				break;
+			case 0x14:	/* 0 1 0 1 */
+				res = add_dataflash(channel, "Atmel AT45DB021B", SZ_256K, 1025, 264, 9);
+				break;
+			case 0x1c:	/* 0 1 1 1 */
+				res = add_dataflash(channel, "Atmel AT45DB041B", SZ_512K, 2048, 264, 9);
+				break;
+			case 0x24:	/* 1 0 0 1 */
+				res = add_dataflash(channel, "Atmel AT45DB081B", SZ_1M, 4096, 264, 9);
+				break;
+			case 0x2c:	/* 1 0 1 1 */
+				res = add_dataflash(channel, "Atmel AT45DB161B", SZ_2M, 4096, 528, 10);
+				break;
+			case 0x34:	/* 1 1 0 1 */
+				res = add_dataflash(channel, "Atmel AT45DB321B", SZ_4M, 8192, 528, 10);
+				break;
+			case 0x3c:	/* 1 1 1 1 */
+				res = add_dataflash(channel, "Atmel AT45DB642", SZ_8M, 8192, 1056, 11);
+				break;
+// Currently unsupported since Atmel removed the "Main Memory Program via Buffer" commands.
+//			case 0x10:	/* 0 1 0 0 */
+//				res = add_dataflash(channel, "Atmel AT45DB1282", SZ_16M, 16384, 1056, 11);
+//				break;
+			default:
+				printk(KERN_ERR "at91_dataflash: Unknown device (%x)\n", status & 0x3c);
+		}
+	}
+	spi_release_bus(channel);
+
+	return res;
+}
+
+static int __init at91_dataflash_init(void)
+{
+	spi_transfer_desc = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
+	if (!spi_transfer_desc)
+		return -ENOMEM;
+
+	/* DataFlash (SPI chip select 0) */
+	at91_dataflash_detect(0);
+
+#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
+	/* DataFlash card (SPI chip select 3) */
+	AT91_CfgPIO_DataFlashCard();
+	at91_dataflash_detect(3);
+#endif
+
+	return 0;
+}
+
+static void __exit at91_dataflash_exit(void)
+{
+	int i;
+
+	for (i = 0; i < DATAFLASH_MAX_DEVICES; i++) {
+		if (mtd_devices[i]) {
+#ifdef CONFIG_MTD_PARTITIONS
+			del_mtd_partitions(mtd_devices[i]);
+#else
+			del_mtd_device(mtd_devices[i]);
+#endif
+			kfree(mtd_devices[i]->priv);
+			kfree(mtd_devices[i]);
+		}
+	}
+	nr_devices = 0;
+	kfree(spi_transfer_desc);
+}
+
+
+module_init(at91_dataflash_init);
+module_exit(at91_dataflash_exit);
+
+MODULE_LICENSE("GPL")
+MODULE_AUTHOR("Andrew Victor")
+MODULE_DESCRIPTION("DataFlash driver for Atmel AT91RM9200")
diff -urN linux-2.6.11-rc5.orig/drivers/mtd/nand/Kconfig linux-2.6.11-rc5/drivers/mtd/nand/Kconfig
--- linux-2.6.11-rc5.orig/drivers/mtd/nand/Kconfig	Fri Feb 25 11:51:37 2005
+++ linux-2.6.11-rc5/drivers/mtd/nand/Kconfig	Fri Feb 25 11:55:46 2005
@@ -203,5 +203,11 @@
 	help
 	  The simulator may simulate verious NAND flash chips for the
 	  MTD nand layer.
- 
+
+config MTD_NAND_AT91
+	bool "AT91 NAND Access (Smart Media)"
+	depends on MTD_NAND && ARCH_AT91RM9200 && EXPERIMENTAL
+	help
+	  Enables Access to the Smart Media Card interface on the AT91RM9200DK
+
 endmenu
diff -urN linux-2.6.11-rc5.orig/drivers/mtd/nand/Makefile linux-2.6.11-rc5/drivers/mtd/nand/Makefile
--- linux-2.6.11-rc5.orig/drivers/mtd/nand/Makefile	Fri Feb 25 11:51:37 2005
+++ linux-2.6.11-rc5/drivers/mtd/nand/Makefile	Fri Feb 25 11:55:46 2005
@@ -20,5 +20,6 @@
 obj-$(CONFIG_MTD_NAND_RTC_FROM4)	+= rtc_from4.o
 obj-$(CONFIG_MTD_NAND_SHARPSL)		+= sharpsl.o
 obj-$(CONFIG_MTD_NAND_NANDSIM)		+= nandsim.o
+obj-$(CONFIG_MTD_NAND_AT91)		+= at91_nand.o
 
 nand-objs = nand_base.o nand_bbt.o
diff -urN linux-2.6.11-rc5.orig/drivers/mtd/nand/at91_nand.c linux-2.6.11-rc5/drivers/mtd/nand/at91_nand.c
--- linux-2.6.11-rc5.orig/drivers/mtd/nand/at91_nand.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/mtd/nand/at91_nand.c	Fri Feb 25 12:27:48 2005
@@ -0,0 +1,303 @@
+/*
+ * drivers/at91/mtd/at91_nand.c
+ *
+ *  Copyright (c) 2003 Rick Bronson
+ *
+ *  Derived from drivers/mtd/nand/autcpu12.c
+ *	 Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
+ *
+ *  Derived from drivers/mtd/spia.c
+ *	 Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/sizes.h>
+
+#include <asm/arch/pio.h>
+
+#define AT91_SMART_MEDIA_ALE (1 << 22)  /* our ALE is AD22 */
+#define AT91_SMART_MEDIA_CLE (1 << 21)  /* our CLE is AD21 */
+/*
+ * MTD structure for AT91 board
+ */
+
+static struct mtd_info *at91_mtd = NULL;
+
+static int at91_fio_base;
+
+#ifdef CONFIG_MTD_PARTITIONS
+
+/*
+ * Define partitions for flash devices
+ */
+
+static struct mtd_partition partition_info32k[] = {
+	{ name: "AT91 NAND partition 1, kernel",
+	  offset:  0,
+	  size:   1 * SZ_1M },
+	{ name: "AT91 NAND partition 2, filesystem",
+	  offset:  1 * SZ_1M,
+	  size:   16 * SZ_1M },
+	{ name: "AT91 NAND partition 3a, storage",
+	  offset: (1 * SZ_1M) + (16 * SZ_1M),
+	  size:   1 * SZ_1M },
+	{ name: "AT91 NAND partition 3b, storage",
+	  offset: (2 * SZ_1M) + (16 * SZ_1M),
+	  size:   1 * SZ_1M },
+	{ name: "AT91 NAND partition 3c, storage",
+	  offset: (3 * SZ_1M) + (16 * SZ_1M),
+	  size:   1 * SZ_1M },
+	{ name: "AT91 NAND partition 3d, storage",
+	  offset: (4 * SZ_1M) + (16 * SZ_1M),
+	  size:   1 * SZ_1M },
+};
+
+static struct mtd_partition partition_info64k[] = {
+	{ name: "AT91 NAND partition 1, kernel",
+	  offset:  0,
+	  size:   1 * SZ_1M },
+	{ name: "AT91 NAND partition 2, filesystem",
+	  offset:  1 * SZ_1M,
+	  size:   16 * SZ_1M },
+	{ name: "AT91 NAND partition 3, storage",
+	  offset: (1 * SZ_1M) + (16 * SZ_1M),
+	  size:   47 * SZ_1M },
+};
+
+#endif
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void at91_hwcontrol (struct mtd_info *mtd, int cmd)
+{
+	struct nand_chip *my_nand = mtd->priv;
+	switch(cmd)
+	{
+	case NAND_CTL_SETCLE:
+		my_nand->IO_ADDR_W = (void __iomem *)(at91_fio_base + AT91_SMART_MEDIA_CLE);
+		break;
+	case NAND_CTL_CLRCLE:
+		my_nand->IO_ADDR_W = (void __iomem *)(at91_fio_base);
+		break;
+	case NAND_CTL_SETALE:
+		my_nand->IO_ADDR_W = (void __iomem *)(at91_fio_base + AT91_SMART_MEDIA_ALE);
+		break;
+	case NAND_CTL_CLRALE:
+		my_nand->IO_ADDR_W = (void __iomem *)(at91_fio_base);
+		break;
+	case NAND_CTL_SETNCE:
+		break;
+	case NAND_CTL_CLRNCE:
+		break;
+	}
+}
+
+/*
+ * Send command to NAND device
+ */
+static void at91_nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
+{
+	register struct nand_chip *my_nand = mtd->priv;
+
+	/* Begin command latch cycle */
+	register unsigned long NAND_IO_ADDR = (unsigned long)(my_nand->IO_ADDR_W + AT91_SMART_MEDIA_CLE);
+
+	/*
+	 * Write out the command to the device.
+	 */
+	if (command != NAND_CMD_SEQIN)
+		writeb (command, NAND_IO_ADDR);
+	else {
+		if (mtd->oobblock == 256 && column >= 256) {
+			column -= 256;
+			writeb (NAND_CMD_RESET, NAND_IO_ADDR);
+			writeb (NAND_CMD_READOOB, NAND_IO_ADDR);
+			writeb (NAND_CMD_SEQIN, NAND_IO_ADDR);
+		}
+		else
+			if (mtd->oobblock == 512 && column >= 256) {
+				if (column < 512) {
+					column -= 256;
+					writeb (NAND_CMD_READ1, NAND_IO_ADDR);
+					writeb (NAND_CMD_SEQIN, NAND_IO_ADDR);
+				} else {
+					column -= 512;
+					writeb (NAND_CMD_READOOB, NAND_IO_ADDR);
+					writeb (NAND_CMD_SEQIN, NAND_IO_ADDR);
+				}
+			} else {
+				writeb (NAND_CMD_READ0, NAND_IO_ADDR);
+				writeb (NAND_CMD_SEQIN, NAND_IO_ADDR);
+			}
+	}
+
+	/* Set ALE and clear CLE to start address cycle */
+	NAND_IO_ADDR = at91_fio_base;
+
+	if (column != -1 || page_addr != -1)
+		NAND_IO_ADDR += AT91_SMART_MEDIA_ALE;
+
+	/* Serially input address */
+	if (column != -1)
+		writeb (column, NAND_IO_ADDR);
+	if (page_addr != -1) {
+		writeb ((unsigned char) (page_addr & 0xff), NAND_IO_ADDR);
+		writeb ((unsigned char) ((page_addr >> 8) & 0xff), NAND_IO_ADDR);
+		/* One more address cycle for higher density devices */
+		if (mtd->size & 0x0c000000) {
+			writeb ((unsigned char) ((page_addr >> 16) & 0x0f), NAND_IO_ADDR);
+		}
+	}
+
+	/* wait until command is processed */
+	while (!my_nand->dev_ready(mtd))
+		;
+}
+
+/*
+ * Read the Device Ready pin.
+ */
+static int at91_device_ready (struct mtd_info *mtd)
+{
+	return AT91_PIO_SmartMedia_RDY();
+}
+/*
+ * Main initialization routine
+ */
+static int __init at91_init (void)
+{
+	struct nand_chip *my_nand;
+	int err = 0;
+
+	/* Allocate memory for MTD device structure and private data */
+	at91_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip), GFP_KERNEL);
+	if (!at91_mtd) {
+		printk ("Unable to allocate AT91 NAND MTD device structure.\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	/* map physical adress */
+	at91_fio_base = (unsigned long) ioremap(AT91_SMARTMEDIA_BASE, SZ_8M);
+	if(!at91_fio_base) {
+		printk("ioremap AT91 NAND failed\n");
+		err = -EIO;
+		goto out_mtd;
+	}
+
+	/* Get pointer to private data */
+	my_nand = (struct nand_chip *) (&at91_mtd[1]);
+
+	/* Initialize structures */
+	memset((char *) at91_mtd, 0, sizeof(struct mtd_info));
+	memset((char *) my_nand, 0, sizeof(struct nand_chip));
+
+	/* Link the private data with the MTD structure */
+	at91_mtd->priv = my_nand;
+
+	/* Set address of NAND IO lines */
+	my_nand->IO_ADDR_R = (void __iomem *)(at91_fio_base);
+	my_nand->IO_ADDR_W = (void __iomem *)(at91_fio_base);
+	my_nand->hwcontrol = at91_hwcontrol;
+	my_nand->dev_ready = at91_device_ready;
+	my_nand->cmdfunc = at91_nand_command;	/* we need our own */
+	my_nand->eccmode = NAND_ECC_SOFT;	/* enable ECC */
+	/* 20 us command delay time */
+	my_nand->chip_delay = 20;
+
+	/* Setup Smart Media, first enable the address range of CS3 */
+	AT91_SYS->EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
+	/* set the bus interface characteristics based on
+	   tDS Data Set up Time 30 - ns
+	   tDH Data Hold Time 20 - ns
+	   tALS ALE Set up Time 20 - ns
+	   16ns at 60 MHz ~= 3  */
+#define AT91C_SM_ID_RWH	(5 << 28)		/* orig = 5 */
+#define AT91C_SM_RWH	(1 << 28)		/* orig = 1 */
+#define AT91C_SM_RWS	(0 << 24)		/* orig = 0 */
+#define AT91C_SM_TDF	(1 << 8)		/* orig = 1 */
+#define AT91C_SM_NWS	(5)			/* orig = 3 */
+	AT91_SYS->EBI_SMC2_CSR[3] = ( AT91C_SM_RWH | AT91C_SM_RWS |
+					 AT91C_SMC2_ACSS_STANDARD |
+					 AT91C_SMC2_DBW_8 | AT91C_SM_TDF |
+					 AT91C_SMC2_WSEN | AT91C_SM_NWS);
+
+	AT91_CfgPIO_SmartMedia();
+
+	if (AT91_PIO_SmartMedia_CardDetect())
+		printk ("No ");
+	printk ("SmartMedia card inserted.\n");
+
+	/* Scan to find existance of the device */
+	if (nand_scan (at91_mtd, 1)) {
+		err = -ENXIO;
+		goto out_ior;
+	}
+
+#ifdef CONFIG_MTD_PARTITIONS
+	/* Register the partitions */
+	switch(at91_mtd->size)
+	{
+	case SZ_32M:
+		err = add_mtd_partitions(at91_mtd, partition_info32k,
+				ARRAY_SIZE (partition_info32k));
+		break;
+	case SZ_64M:
+		err = add_mtd_partitions(at91_mtd, partition_info64k,
+				ARRAY_SIZE (partition_info64k));
+		break;
+	default:
+		printk ("Unsupported SmartMedia device\n");
+		err = -ENXIO;
+		goto out_cac;
+	}
+#else
+	err = add_mtd_device(at91_mtd);
+#endif
+	goto out;
+
+ out_cac:
+ out_ior:
+	iounmap((void *)at91_fio_base);
+ out_mtd:
+	kfree (at91_mtd);
+ out:
+	return err;
+}
+
+/*
+ * Clean up routine
+ */
+static void __exit at91_cleanup (void)
+{
+	/* Unregister partitions */
+	del_mtd_partitions(at91_mtd);
+
+	/* Unregister the device */
+	del_mtd_device (at91_mtd);
+
+	/* unmap physical adress */
+	iounmap((void *)at91_fio_base);
+
+	/* Free the MTD device structure */
+	kfree (at91_mtd);
+}
+
+module_init(at91_init);
+module_exit(at91_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Rick Bronson");
+MODULE_DESCRIPTION("Glue layer for SmartMediaCard on ATMEL AT91RM9200");
diff -urN linux-2.6.11-rc5.orig/drivers/net/arm/Kconfig linux-2.6.11-rc5/drivers/net/arm/Kconfig
--- linux-2.6.11-rc5.orig/drivers/net/arm/Kconfig	Fri Feb 25 11:48:46 2005
+++ linux-2.6.11-rc5/drivers/net/arm/Kconfig	Fri Feb 25 11:55:46 2005
@@ -44,3 +44,18 @@
 	  will generate a suitable hw address based on the board serial
 	  number (MTD support is required for this). Otherwise you will
 	  need to set a suitable hw address using ifconfig.
+
+config ARM_AT91_ETHER
+	tristate "AT91RM9200 Ethernet support"
+	depends on NET_ETHERNET && ARM && ARCH_AT91RM9200
+	select CRC32
+	select MII
+	help
+	  If you wish to compile a kernel for the AT91RM9200 and enable
+	  ethernet support, then you should always answer Y to this.
+
+config ARM_AT91_ETHER_RMII
+	bool "RMII interface"
+	depends on ARM_AT91_ETHER
+	help
+	  If the interface to the Ethernet PHY is RMII, enable this.
diff -urN linux-2.6.11-rc5.orig/drivers/net/arm/Makefile linux-2.6.11-rc5/drivers/net/arm/Makefile
--- linux-2.6.11-rc5.orig/drivers/net/arm/Makefile	Sun Apr  4 05:37:27 2004
+++ linux-2.6.11-rc5/drivers/net/arm/Makefile	Fri Feb 25 11:55:46 2005
@@ -8,3 +8,4 @@
 obj-$(CONFIG_ARM_ETHERH)	+= etherh.o
 obj-$(CONFIG_ARM_ETHER3)	+= ether3.o
 obj-$(CONFIG_ARM_ETHER1)	+= ether1.o
+obj-$(CONFIG_ARM_AT91_ETHER)	+= at91_ether.o
diff -urN linux-2.6.11-rc5.orig/drivers/net/arm/at91_ether.c linux-2.6.11-rc5/drivers/net/arm/at91_ether.c
--- linux-2.6.11-rc5.orig/drivers/net/arm/at91_ether.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/net/arm/at91_ether.c	Fri Feb 25 12:26:22 2005
@@ -0,0 +1,968 @@
+/*
+ * Ethernet driver for the Atmel AT91RM9200 (Thunder)
+ *
+ * (c) SAN People (Pty) Ltd
+ *
+ * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
+ * Initial version by Rick Bronson 01/11/2003
+ *
+ * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
+ *   (Polaroid Corporation)
+ *
+ * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/config.h>
+#include <linux/mii.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <asm/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/crc32.h>
+#include <asm/uaccess.h>
+#include <linux/ethtool.h>
+
+#include <asm/arch/AT91RM9200_EMAC.h>
+#include <asm/arch/pio.h>
+#include "at91_ether.h"
+
+static struct net_device *at91_dev = NULL;
+
+/* ........................... PHY INTERFACE ........................... */
+
+/*
+ * Enable the MDIO bit in MAC control register
+ * When not called from an interrupt-handler, access to the PHY must be
+ *  protected by a spinlock.
+ */
+static void enable_mdi(AT91PS_EMAC regs)
+{
+	regs->EMAC_CTL |= AT91C_EMAC_MPE;	/* enable management port */
+}
+
+/*
+ * Disable the MDIO bit in the MAC control register
+ */
+static void disable_mdi(AT91PS_EMAC regs)
+{
+	regs->EMAC_CTL &= ~AT91C_EMAC_MPE;	/* disable management port */
+}
+
+/*
+ * Write value to the a PHY register
+ * Note: MDI interface is assumed to already have been enabled.
+ */
+static void write_phy(AT91PS_EMAC regs, unsigned char phy_addr, unsigned char address, unsigned int value)
+{
+	regs->EMAC_MAN = (AT91C_EMAC_HIGH | AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W
+		| ((phy_addr & 0x1f) << 23) | (address << 18)) + (value & 0xffff);
+
+	/* Wait until IDLE bit in Network Status register is cleared */
+	// TODO: Enforce some maximum loop-count?
+	while (!(regs->EMAC_SR & AT91C_EMAC_IDLE)) { barrier(); }
+}
+
+/*
+ * Read value stored in a PHY register.
+ * Note: MDI interface is assumed to already have been enabled.
+ */
+static void read_phy(AT91PS_EMAC regs, unsigned char phy_addr, unsigned char address, unsigned int *value)
+{
+	regs->EMAC_MAN = AT91C_EMAC_HIGH | AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_R
+		| ((phy_addr & 0x1f) << 23) | (address << 18);
+
+	/* Wait until IDLE bit in Network Status register is cleared */
+	// TODO: Enforce some maximum loop-count?
+	while (!(regs->EMAC_SR & AT91C_EMAC_IDLE)) { barrier(); }
+
+	*value = (regs->EMAC_MAN & 0x0000ffff);
+}
+
+/* ........................... PHY MANAGEMENT .......................... */
+
+/*
+ * Access the PHY to determine the current Link speed and Mode, and update the
+ * MAC accordingly.
+ * If no link or auto-negotiation is busy, then no changes are made.
+ * Returns:  0 : OK
+ *          -1 : No link
+ *          -2 : AutoNegotiation still in progress
+ */
+static int update_linkspeed(struct net_device *dev, AT91PS_EMAC regs) {
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	unsigned int bmsr, bmcr, lpa, mac_cfg;
+	unsigned int speed, duplex;
+
+	/* Link status is latched, so read twice to get current value */
+	read_phy(regs, lp->phy_address, MII_BMSR, &bmsr);
+	read_phy(regs, lp->phy_address, MII_BMSR, &bmsr);
+	if (!(bmsr & BMSR_LSTATUS)) return -1;			/* no link */
+
+	read_phy(regs, lp->phy_address, MII_BMCR, &bmcr);
+	if (bmcr & BMCR_ANENABLE) {				/* AutoNegotiation is enabled */
+		if (!(bmsr & BMSR_ANEGCOMPLETE)) return -2;	/* auto-negotitation in progress */
+
+		read_phy(regs, lp->phy_address, MII_LPA, &lpa);
+		if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
+		else speed = SPEED_10;
+		if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
+		else duplex = DUPLEX_HALF;
+	} else {
+		speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
+		duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
+	}
+
+	/* Update the MAC */
+	mac_cfg = regs->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+	if (speed == SPEED_100) {
+		if (duplex == DUPLEX_FULL)		/* 100 Full Duplex */
+			regs->EMAC_CFG = mac_cfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		else					/* 100 Half Duplex */
+			regs->EMAC_CFG = mac_cfg | AT91C_EMAC_SPD;
+	} else {
+		if (duplex == DUPLEX_FULL)		/* 10 Full Duplex */
+			regs->EMAC_CFG = mac_cfg | AT91C_EMAC_FD;
+		else					/* 10 Half Duplex */
+			regs->EMAC_CFG = mac_cfg;
+	}
+
+	printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
+	return 0;
+}
+
+/*
+ * Handle interrupts from the PHY
+ */
+static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	struct net_device *dev = (struct net_device *) dev_id;
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	AT91PS_EMAC emac = (AT91PS_EMAC) dev->base_addr;
+	int status;
+	unsigned int phy;
+
+	enable_mdi(emac);
+	if (lp->phy_type == MII_DM9161_ID)
+		read_phy(emac, lp->phy_address, MII_DSINTR_REG, &phy);	/* ack interrupt in Davicom PHY */
+	else if (lp->phy_type == MII_LXT971A_ID)
+		read_phy(emac, lp->phy_address, MII_ISINTS_REG, &phy);	/* ack interrupt in Intel PHY */
+	else if (lp->phy_type == MII_BCM5221_ID)
+		read_phy(emac, lp->phy_address, MII_BCMINTR_REG, &phy);	/* ack interrupt in Broadcom PHY */
+		
+	status = AT91_SYS->PIOC_ISR;		/* acknowledge interrupt in PIO */
+
+	status = update_linkspeed(dev, emac);
+	if (status == -1) {			/* link is down */
+		netif_carrier_off(dev);
+		printk(KERN_INFO "%s: Link down.\n", dev->name);
+	} else if (status == -2) {		/* auto-negotiation in progress */
+		/* Do nothing - another interrupt generated when negotiation complete */
+	} else {				/* link is operational */
+		netif_carrier_on(dev);
+	}
+	disable_mdi(emac);
+	
+	return IRQ_HANDLED;
+}
+
+/*
+ * Initialize and enable the PHY interrupt when link-state changes
+ */
+static void enable_phyirq(struct net_device *dev, AT91PS_EMAC regs)
+{
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	unsigned int dsintr, status;
+	
+	if (lp->phy_type == MII_RTL8201_ID)	/* RTL8201 does not have an interrupt */
+		return;
+
+	// TODO: Check error code.  Really need a generic PIO (interrupt)
+	// layer since we're really only interested in the PC4 (DK) or PC2 (CSB337, CSB637) line.
+	(void) request_irq(AT91C_ID_PIOC, at91ether_phy_interrupt, 0, dev->name, dev);
+
+	status = AT91_SYS->PIOC_ISR;		/* clear any pending PIO interrupts */
+#if defined(CONFIG_MACH_CSB337) || defined(CONFIG_MACH_CSB637)
+	AT91_SYS->PIOC_IER = AT91C_PIO_PC2;	/* Enable interrupt */
+#else
+	AT91_SYS->PIOC_IER = AT91C_PIO_PC4;	/* Enable interrupt */
+#endif
+
+	spin_lock_irq(&lp->lock);
+	enable_mdi(regs);
+		
+	if (lp->phy_type == MII_DM9161_ID) {		/* for Davicom PHY */
+		read_phy(regs, lp->phy_address, MII_DSINTR_REG, &dsintr);
+		dsintr = dsintr & ~0xf00;		/* clear bits 8..11 */
+		write_phy(regs, lp->phy_address, MII_DSINTR_REG, dsintr);
+	}
+	else if (lp->phy_type == MII_LXT971A_ID) {	/* for Intel PHY */
+		read_phy(regs, lp->phy_address, MII_ISINTE_REG, &dsintr);
+		dsintr = dsintr | 0xf2;			/* set bits 1, 4..7 */
+		write_phy(regs, lp->phy_address, MII_ISINTE_REG, dsintr);
+	}
+	else if (lp->phy_type == MII_BCM5221_ID) {	/* for Broadcom PHY */
+		dsintr = (1 << 15) | ( 1 << 14);
+		write_phy(regs, lp->phy_address, MII_BCMINTR_REG, dsintr);
+	}
+		
+	disable_mdi(regs);
+	spin_unlock_irq(&lp->lock);
+}
+
+/*
+ * Disable the PHY interrupt
+ */
+static void disable_phyirq(struct net_device *dev, AT91PS_EMAC regs)
+{
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	unsigned int dsintr;
+
+	if (lp->phy_type == MII_RTL8201_ID) 	/* RTL8201 does not have an interrupt */
+		return;
+
+	spin_lock_irq(&lp->lock);
+	enable_mdi(regs);
+
+	if (lp->phy_type == MII_DM9161_ID) {		/* for Davicom PHY */
+		read_phy(regs, lp->phy_address, MII_DSINTR_REG, &dsintr);
+		dsintr = dsintr | 0xf00;			/* set bits 8..11 */
+		write_phy(regs, lp->phy_address, MII_DSINTR_REG, dsintr);
+	}
+	else if (lp->phy_type == MII_LXT971A_ID) {	/* for Intel PHY */
+		read_phy(regs, lp->phy_address, MII_ISINTE_REG, &dsintr);
+		dsintr = dsintr & ~0xf2;			/* clear bits 1, 4..7 */
+		write_phy(regs, lp->phy_address, MII_ISINTE_REG, dsintr);
+	}
+	else if (lp->phy_type == MII_BCM5221_ID) {	/* for Broadcom PHY */
+		read_phy(regs, lp->phy_address, MII_BCMINTR_REG, &dsintr);
+		dsintr = ~(1 << 14);
+		write_phy(regs, lp->phy_address, MII_BCMINTR_REG, dsintr);
+	}
+
+	disable_mdi(regs);
+	spin_unlock_irq(&lp->lock);
+
+#if defined(CONFIG_MACH_CSB337) || defined(CONFIG_MACH_CSB637)
+	AT91_SYS->PIOC_IDR = AT91C_PIO_PC2;		/* Disable interrupt */
+#else
+	AT91_SYS->PIOC_IDR = AT91C_PIO_PC4;		/* Disable interrupt */
+#endif
+	free_irq(AT91C_ID_PIOC, dev);			/* Free interrupt handler */
+}
+
+/*
+ * Perform a software reset of the PHY.
+ */
+#if(0)
+static void reset_phy(struct net_device *dev, AT91PS_EMAC regs)
+{
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	unsigned int bmcr;
+
+	spin_lock_irq(&lp->lock);
+	enable_mdi(regs);
+
+	/* Perform PHY reset */
+	write_phy(regs, lp->phy_address, MII_BMCR, BMCR_RESET);
+
+	/* Wait until PHY reset is complete */
+	do {
+		read_phy(regs, lp->phy_address, MII_BMCR, &bmcr);
+	} while (!(bmcr && BMCR_RESET));
+
+	disable_mdi(regs);
+	spin_unlock_irq(&lp->lock);
+}
+
+#endif
+/* ......................... ADDRESS MANAGEMENT ........................ */
+
+/*
+ * Set the ethernet MAC address in dev->dev_addr
+ */
+static void get_mac_address(struct net_device *dev) {
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+	char addr[6];
+	unsigned int hi, lo;
+
+	/* Check if bootloader set address in Specific-Address 1 */
+	hi = regs->EMAC_SA1H;
+	lo = regs->EMAC_SA1L;
+#ifdef CONFIG_MACH_CSB337
+	addr[5] = (lo & 0xff);			/* The CSB337 bootloader stores the MAC the wrong-way around */
+	addr[4] = (lo & 0xff00) >> 8;
+	addr[3] = (lo & 0xff0000) >> 16;
+	addr[2] = (lo & 0xff000000) >> 24;
+	addr[1] = (hi & 0xff);
+	addr[0] = (hi & 0xff00) >> 8;
+#else
+	addr[0] = (lo & 0xff);
+	addr[1] = (lo & 0xff00) >> 8;
+	addr[2] = (lo & 0xff0000) >> 16;
+	addr[3] = (lo & 0xff000000) >> 24;
+	addr[4] = (hi & 0xff);
+	addr[5] = (hi & 0xff00) >> 8;
+#endif
+
+	if (is_valid_ether_addr(addr)) {
+		memcpy(dev->dev_addr, &addr, 6);
+		return;
+	}
+
+	/* Check if bootloader set address in Specific-Address 2 */
+	hi = regs->EMAC_SA2H;
+	lo = regs->EMAC_SA2L;
+#ifdef CONFIG_MACH_CSB337
+	addr[5] = (lo & 0xff);			/* The CSB337 bootloader stores the MAC the wrong-way around */
+	addr[4] = (lo & 0xff00) >> 8;
+	addr[3] = (lo & 0xff0000) >> 16;
+	addr[2] = (lo & 0xff000000) >> 24;
+	addr[1] = (hi & 0xff);
+	addr[0] = (hi & 0xff00) >> 8;
+#else
+	addr[0] = (lo & 0xff);
+	addr[1] = (lo & 0xff00) >> 8;
+	addr[2] = (lo & 0xff0000) >> 16;
+	addr[3] = (lo & 0xff000000) >> 24;
+	addr[4] = (hi & 0xff);
+	addr[5] = (hi & 0xff00) >> 8;
+#endif
+
+	if (is_valid_ether_addr(addr)) {
+		memcpy(dev->dev_addr, &addr, 6);
+		return;
+	}
+}
+
+/*
+ * Program the hardware MAC address from dev->dev_addr.
+ */
+static void update_mac_address(struct net_device *dev)
+{
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+
+	regs->EMAC_SA1L = (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]);
+	regs->EMAC_SA1H = (dev->dev_addr[5] << 8) | (dev->dev_addr[4]);
+
+	regs->EMAC_SA2L = 0;
+	regs->EMAC_SA2H = 0;
+}
+
+/*
+ * Store the new hardware address in dev->dev_addr, and update the MAC.
+ */
+static int set_mac_address(struct net_device *dev, void* addr)
+{
+	struct sockaddr *address = addr;
+
+	if (!is_valid_ether_addr(address->sa_data))
+		return -EADDRNOTAVAIL;
+
+	memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
+	update_mac_address(dev);
+
+	printk("%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
+		dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
+		dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
+
+	return 0;
+}
+
+/*
+ * Add multicast addresses to the internal multicast-hash table.
+ */
+static void at91ether_sethashtable(struct net_device *dev, AT91PS_EMAC regs)
+{
+	struct dev_mc_list *curr;
+	unsigned char mc_filter[2];
+	unsigned int i, bitnr;
+
+	mc_filter[0] = mc_filter[1] = 0;
+
+	curr = dev->mc_list;
+	for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
+		if (!curr) break;	/* unexpected end of list */
+
+		bitnr = ether_crc(ETH_ALEN, curr->dmi_addr) >> 26;
+		mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
+	}
+
+	regs->EMAC_HSH = mc_filter[1];
+	regs->EMAC_HSL = mc_filter[0];
+}
+
+/*
+ * Enable/Disable promiscuous and multicast modes.
+ */
+static void at91ether_set_rx_mode(struct net_device *dev)
+{
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+
+	if (dev->flags & IFF_PROMISC) {			/* Enable promiscuous mode */
+		regs->EMAC_CFG |= AT91C_EMAC_CAF;
+	} else if (dev->flags & (~IFF_PROMISC)) {	/* Disable promiscuous mode */
+		regs->EMAC_CFG &= ~AT91C_EMAC_CAF;
+	}
+
+	if (dev->flags & IFF_ALLMULTI) {		/* Enable all multicast mode */
+		regs->EMAC_HSH = -1;
+		regs->EMAC_HSL = -1;
+		regs->EMAC_CFG |= AT91C_EMAC_MTI;
+	} else if (dev->mc_count > 0) {			/* Enable specific multicasts */
+		at91ether_sethashtable(dev, regs);
+		regs->EMAC_CFG |= AT91C_EMAC_MTI;
+	} else if (dev->flags & (~IFF_ALLMULTI)) {	/* Disable all multicast mode */
+		regs->EMAC_HSH = 0;
+		regs->EMAC_HSL = 0;
+		regs->EMAC_CFG &= ~AT91C_EMAC_MTI;
+	}
+}
+
+/* ............................... IOCTL ............................... */
+
+static int mdio_read(struct net_device *dev, int phy_id, int location)
+{
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+	unsigned int value;
+
+	read_phy(regs, phy_id, location, &value);
+	return value;
+}
+
+static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
+{
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+
+	write_phy(regs, phy_id, location, value);
+}
+
+/*
+ * ethtool support.
+ */
+static int at91ether_ethtool_ioctl (struct net_device *dev, void *useraddr)
+{
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+	u32 ethcmd;
+	int res = 0;
+
+	if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
+		return -EFAULT;
+
+	spin_lock_irq(&lp->lock);
+	enable_mdi(regs);
+
+	switch (ethcmd) {
+	case ETHTOOL_GSET: {
+		struct ethtool_cmd ecmd = { ETHTOOL_GSET };
+		res = mii_ethtool_gset(&lp->mii, &ecmd);
+		if (lp->phy_media == PORT_FIBRE) {		/* override media type since mii.c doesn't know */
+			ecmd.supported = SUPPORTED_FIBRE;
+			ecmd.port = PORT_FIBRE;
+		}
+		if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
+			res = -EFAULT;
+		break;
+	}
+	case ETHTOOL_SSET: {
+		struct ethtool_cmd ecmd;
+		if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
+			res = -EFAULT;
+		else
+			res = mii_ethtool_sset(&lp->mii, &ecmd);
+		break;
+	}
+	case ETHTOOL_NWAY_RST: {
+		res = mii_nway_restart(&lp->mii);
+		break;
+	}
+	case ETHTOOL_GLINK: {
+		struct ethtool_value edata = { ETHTOOL_GLINK };
+		edata.data = mii_link_ok(&lp->mii);
+		if (copy_to_user(useraddr, &edata, sizeof(edata)))
+			res = -EFAULT;
+		break;
+	}
+	default:
+		res = -EOPNOTSUPP;
+	}
+
+	disable_mdi(regs);
+	spin_unlock_irq(&lp->lock);
+
+	return res;
+}
+
+/*
+ * User-space ioctl interface.
+ */
+static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+	switch(cmd) {
+	case SIOCETHTOOL:
+		return at91ether_ethtool_ioctl(dev, (void *) rq->ifr_data);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+/* ................................ MAC ................................ */
+
+/*
+ * Initialize and start the Receiver and Transmit subsystems
+ */
+static void at91ether_start(struct net_device *dev)
+{
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	int i;
+	struct recv_desc_bufs *dlist, *dlist_phys;
+
+	dlist = lp->dlist;
+	dlist_phys = lp->dlist_phys;
+
+	for (i = 0; i < MAX_RX_DESCR; i++) {
+		dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
+		dlist->descriptors[i].size = 0;
+	}
+
+	/* Set the Wrap bit on the last descriptor */
+	dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
+
+	/* Reset buffer index */
+	lp->rxBuffIndex = 0;
+
+	/* Program address of descriptor list in Rx Buffer Queue register */
+	regs->EMAC_RBQP = (AT91_REG) dlist_phys;
+
+	/* Enable Receive and Transmit */
+	regs->EMAC_CTL |= (AT91C_EMAC_RE | AT91C_EMAC_TE);
+}
+
+/*
+ * Open the ethernet interface
+ */
+static int at91ether_open(struct net_device *dev)
+{
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+
+        if (!is_valid_ether_addr(dev->dev_addr))
+        	return -EADDRNOTAVAIL;
+
+	AT91_SYS->PMC_PCER = 1 << AT91C_ID_EMAC;	/* Re-enable Peripheral clock */
+	regs->EMAC_CTL |= AT91C_EMAC_CSR;		/* Clear internal statistics */
+
+	/* Update the MAC address (incase user has changed it) */
+	update_mac_address(dev);
+
+	/* Enable PHY interrupt */
+	enable_phyirq(dev, regs);
+
+	/* Enable MAC interrupts */
+	regs->EMAC_IER = AT91C_EMAC_RCOM | AT91C_EMAC_RBNA
+			| AT91C_EMAC_TUND | AT91C_EMAC_RTRY | AT91C_EMAC_TCOM
+			| AT91C_EMAC_ROVR | AT91C_EMAC_HRESP;
+
+	/* Determine current link speed */
+	spin_lock_irq(&lp->lock);
+	enable_mdi(regs);
+	(void) update_linkspeed(dev, regs);
+	disable_mdi(regs);
+	spin_unlock_irq(&lp->lock);
+
+	at91ether_start(dev);
+	netif_start_queue(dev);
+	return 0;
+}
+
+/*
+ * Close the interface
+ */
+static int at91ether_close(struct net_device *dev)
+{
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+
+	/* Disable Receiver and Transmitter */
+	regs->EMAC_CTL &= ~(AT91C_EMAC_TE | AT91C_EMAC_RE);
+
+	/* Disable PHY interrupt */
+	disable_phyirq(dev, regs);
+
+	/* Disable MAC interrupts */
+	regs->EMAC_IDR = AT91C_EMAC_RCOM | AT91C_EMAC_RBNA
+			| AT91C_EMAC_TUND | AT91C_EMAC_RTRY | AT91C_EMAC_TCOM
+			| AT91C_EMAC_ROVR | AT91C_EMAC_HRESP;
+
+	netif_stop_queue(dev);
+
+	AT91_SYS->PMC_PCDR = 1 << AT91C_ID_EMAC;	/* Disable Peripheral clock */
+
+	return 0;
+}
+
+/*
+ * Transmit packet.
+ */
+static int at91ether_tx(struct sk_buff *skb, struct net_device *dev)
+{
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+
+	if (regs->EMAC_TSR & AT91C_EMAC_BNQ) {
+		netif_stop_queue(dev);
+
+		/* Store packet information (to free when Tx completed) */
+		lp->skb = skb;
+		lp->skb_length = skb->len;
+		lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
+		lp->stats.tx_bytes += skb->len;
+
+		/* Set address of the data in the Transmit Address register */
+		regs->EMAC_TAR = lp->skb_physaddr;
+		/* Set length of the packet in the Transmit Control register */
+		regs->EMAC_TCR = skb->len;
+
+		dev->trans_start = jiffies;
+	} else {
+		printk(KERN_ERR "at91_ether.c: at91ether_tx() called, but device is busy!\n");
+		return 1;	/* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
+				on this skb, he also reports -ENETDOWN and printk's, so either
+				we free and return(0) or don't free and return 1 */
+	}
+
+	return 0;
+}
+
+/*
+ * Update the current statistics from the internal statistics registers.
+ */
+static struct net_device_stats *at91ether_stats(struct net_device *dev)
+{
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr;
+	int ale, lenerr, seqe, lcol, ecol;
+
+	if (netif_running(dev)) {
+		lp->stats.rx_packets += regs->EMAC_OK;			/* Good frames received */
+		ale = regs->EMAC_ALE;
+		lp->stats.rx_frame_errors += ale;			/* Alignment errors */
+		lenerr = regs->EMAC_ELR + regs->EMAC_USF;
+		lp->stats.rx_length_errors += lenerr;			/* Excessive Length or Undersize Frame error */
+		seqe = regs->EMAC_SEQE;
+		lp->stats.rx_crc_errors += seqe;			/* CRC error */
+		lp->stats.rx_fifo_errors += regs->EMAC_DRFC;		/* Receive buffer not available */
+		lp->stats.rx_errors += (ale + lenerr + seqe + regs->EMAC_CDE + regs->EMAC_RJB);
+
+		lp->stats.tx_packets += regs->EMAC_FRA;			/* Frames successfully transmitted */
+		lp->stats.tx_fifo_errors += regs->EMAC_TUE;		/* Transmit FIFO underruns */
+		lp->stats.tx_carrier_errors += regs->EMAC_CSE;		/* Carrier Sense errors */
+		lp->stats.tx_heartbeat_errors += regs->EMAC_SQEE;	/* Heartbeat error */
+
+		lcol = regs->EMAC_LCOL;
+		ecol = regs->EMAC_ECOL;
+		lp->stats.tx_window_errors += lcol;			/* Late collisions */
+		lp->stats.tx_aborted_errors += ecol;			/* 16 collisions */
+
+		lp->stats.collisions += (regs->EMAC_SCOL + regs->EMAC_MCOL + lcol + ecol);
+	}
+	return &lp->stats;
+}
+
+/*
+ * Extract received frame from buffer descriptors and sent to upper layers.
+ * (Called from interrupt context)
+ */
+static void at91ether_rx(struct net_device *dev)
+{
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	struct recv_desc_bufs *dlist;
+	unsigned char *p_recv;
+	struct sk_buff *skb;
+	unsigned int pktlen;
+
+	dlist = lp->dlist;
+	while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
+		p_recv = dlist->recv_buf[lp->rxBuffIndex];
+		pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff;	/* Length of frame including FCS */
+		skb = alloc_skb(pktlen + 2, GFP_ATOMIC);
+		if (skb != NULL) {
+			skb_reserve(skb, 2);
+			memcpy(skb_put(skb, pktlen), p_recv, pktlen);
+
+			skb->dev = dev;
+			skb->protocol = eth_type_trans(skb, dev);
+			skb->len = pktlen;
+			dev->last_rx = jiffies;
+			lp->stats.rx_bytes += pktlen;
+			netif_rx(skb);
+		}
+		else {
+			lp->stats.rx_dropped += 1;
+			printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
+		}
+
+		if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
+			lp->stats.multicast++;
+
+		dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE;	/* reset ownership bit */
+		if (lp->rxBuffIndex == MAX_RX_DESCR-1)				/* wrap after last buffer */
+			lp->rxBuffIndex = 0;
+		else
+			lp->rxBuffIndex++;
+	}
+}
+
+/*
+ * MAC interrupt handler
+ */
+static irqreturn_t at91ether_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	struct net_device *dev = (struct net_device *) dev_id;
+	struct at91_private *lp = (struct at91_private *) dev->priv;
+	AT91PS_EMAC emac = (AT91PS_EMAC) dev->base_addr;
+	unsigned long intstatus;
+
+	/* MAC Interrupt Status register indicates what interrupts are pending.
+	   It is automatically cleared once read. */
+	intstatus = emac->EMAC_ISR;
+
+	if (intstatus & AT91C_EMAC_RCOM)		/* Receive complete */
+		at91ether_rx(dev);
+
+	if (intstatus & AT91C_EMAC_TCOM) {		/* Transmit complete */
+		/* The TCOM bit is set even if the transmission failed. */
+		if (intstatus & (AT91C_EMAC_TUND | AT91C_EMAC_RTRY))
+			lp->stats.tx_errors += 1;
+		
+		if (lp->skb) {
+			dev_kfree_skb_irq(lp->skb);
+			lp->skb = NULL;
+			dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
+		}
+		netif_wake_queue(dev);
+	}
+
+	/* Work-around for Errata #11 */
+	if (intstatus & AT91C_EMAC_RBNA) {
+		emac->EMAC_CTL &= ~AT91C_EMAC_RE;
+		emac->EMAC_CTL |= AT91C_EMAC_RE;
+	}
+	
+	if (intstatus & AT91C_EMAC_ROVR)
+		printk("%s: ROVR error\n", dev->name);
+		
+	return IRQ_HANDLED;
+}
+
+/*
+ * Initialize the ethernet interface
+ */
+static int at91ether_setup(unsigned long phy_type, unsigned short phy_address)
+{
+	struct net_device *dev;
+	struct at91_private *lp;
+	AT91PS_EMAC regs;
+	unsigned int val;
+	int res;
+
+	if (at91_dev)			/* already initialized */
+		return 0;
+
+	dev = alloc_etherdev(sizeof(struct at91_private));
+	if (!dev)
+		return -ENOMEM;
+	
+	dev->base_addr = AT91C_VA_BASE_EMAC;
+	dev->irq = AT91C_ID_EMAC;
+	SET_MODULE_OWNER(dev);
+
+	/* Install the interrupt handler */
+	if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
+		free_netdev(dev);
+		return -EBUSY;
+	}
+
+	/* Allocate memory for DMA Receive descriptors */
+	lp = (struct at91_private *)dev->priv;
+	lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
+	if (lp->dlist == NULL) {
+		free_irq(dev->irq, dev);
+		free_netdev(dev);
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&lp->lock);
+
+	ether_setup(dev);
+	dev->open = at91ether_open;
+	dev->stop = at91ether_close;
+	dev->hard_start_xmit = at91ether_tx;
+	dev->get_stats = at91ether_stats;
+	dev->set_multicast_list = at91ether_set_rx_mode;
+	dev->do_ioctl = at91ether_ioctl;
+	dev->set_mac_address = set_mac_address;
+
+	get_mac_address(dev);		/* Get ethernet address and store it in dev->dev_addr */
+	update_mac_address(dev);	/* Program ethernet address into MAC */
+
+	regs = (AT91PS_EMAC) dev->base_addr;
+	regs->EMAC_CTL = 0;
+
+#ifdef CONFIG_ARM_AT91_ETHER_RMII
+	regs->EMAC_CFG = AT91C_EMAC_BIG | AT91C_EMAC_RMII;
+#else
+	regs->EMAC_CFG = AT91C_EMAC_BIG;
+#endif
+	if ((phy_type == MII_LXT971A_ID) || (phy_type == MII_RTL8201_ID) || (phy_type == MII_BCM5221_ID))
+		regs->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;	/* MDIO clock = system clock/64 */
+
+	if (phy_type == MII_DM9161_ID) {
+		spin_lock_irq(&lp->lock);
+		enable_mdi(regs);
+
+		read_phy(regs, phy_address, MII_DSCR_REG, &val);
+		if ((val & (1 << 10)) == 0)			/* DSCR bit 10 is 0 -- fiber mode */
+			lp->phy_media = PORT_FIBRE;
+
+		disable_mdi(regs);
+		spin_unlock_irq(&lp->lock);
+	}
+
+	lp->mii.dev = dev;		/* Support for ethtool */
+	lp->mii.mdio_read = mdio_read;
+	lp->mii.mdio_write = mdio_write;
+	
+	lp->phy_type = phy_type;	/* Type of PHY connected */
+	lp->phy_address = phy_address;	/* MDI address of PHY */
+
+	/* Register the network interface */
+	res = register_netdev(dev);
+	if (res) {
+		free_irq(dev->irq, dev);
+		free_netdev(dev);
+		dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
+		return res;
+	}
+	at91_dev = dev;
+
+	/* Determine current link speed */
+	spin_lock_irq(&lp->lock);
+	enable_mdi(regs);
+	(void) update_linkspeed(dev, regs);
+	disable_mdi(regs);
+	spin_unlock_irq(&lp->lock);
+
+	/* Display ethernet banner */
+	printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%02x:%02x:%02x:%02x:%02x:%02x)\n",
+		dev->name, (uint) dev->base_addr, dev->irq,
+		regs->EMAC_CFG & AT91C_EMAC_SPD ? "100-" : "10-",
+		regs->EMAC_CFG & AT91C_EMAC_FD ? "FullDuplex" : "HalfDuplex",
+		dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
+		dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
+	if (phy_type == MII_DM9161_ID)
+		printk(KERN_INFO "%s: Davicom 9196 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
+	else if (phy_type == MII_LXT971A_ID)
+		printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
+	else if (phy_type == MII_RTL8201_ID)
+		printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
+	else if (phy_type == MII_BCM5221_ID)
+		printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
+
+	return 0;
+}
+
+/*
+ * Detect MAC and PHY and perform initialization
+ */
+static int at91ether_probe(void)
+{
+	AT91PS_EMAC regs = (AT91PS_EMAC) AT91C_VA_BASE_EMAC;
+	unsigned int phyid1, phyid2;
+	int detected = -1;
+	unsigned short phy_address = 0;
+
+	/* Configure the hardware - RMII vs MII mode */
+#ifdef CONFIG_ARM_AT91_ETHER_RMII
+	AT91_CfgPIO_EMAC_RMII();
+#else
+	AT91_CfgPIO_EMAC_MII();
+#endif
+
+	AT91_CfgPIO_EMAC_PHY();				/* Configure PHY interrupt */
+	AT91_SYS->PMC_PCER = 1 << AT91C_ID_EMAC;	/* Enable Peripheral clock */
+
+	while (phy_address < 32) {
+		/* Read the PHY ID registers */
+		enable_mdi(regs);
+		read_phy(regs, phy_address, MII_PHYSID1, &phyid1);
+		read_phy(regs, phy_address, MII_PHYSID2, &phyid2);
+		disable_mdi(regs);
+
+		/* Davicom 9161: PHY_ID1 = 0x181  PHY_ID2 = B881 */
+		if (((phyid1 << 16) | (phyid2 & 0xfff0)) == MII_DM9161_ID) {
+			detected = at91ether_setup(MII_DM9161_ID, phy_address);
+			break;
+		}
+		/* Intel LXT971A: PHY_ID1 = 0x13  PHY_ID2 = 78E0 */
+		else if (((phyid1 << 16) | (phyid2 & 0xfff0)) == MII_LXT971A_ID) {
+			detected = at91ether_setup(MII_LXT971A_ID, phy_address);
+			break;
+		}
+		/* Realtek RTL8201: PHY_ID1 = 0  PHY_ID2 = 0x8201 */
+		else if (((phyid1 << 16) | (phyid2 & 0xfff0)) == MII_RTL8201_ID) {
+			detected = at91ether_setup(MII_RTL8201_ID, phy_address);
+			break;
+		}
+		/* Broadcom BCM5221: PHY_ID1 = 0x40  PHY_ID2 = 0x61e0 */
+		else if (((phyid1 << 16) | (phyid2 & 0xfff0)) == MII_BCM5221_ID) {
+			detected = at91ether_setup(MII_BCM5221_ID, phy_address);
+			break;
+		}
+		
+		phy_address++;
+	}
+
+	AT91_SYS->PMC_PCDR = 1 << AT91C_ID_EMAC;	/* Disable Peripheral clock */
+
+	return detected;
+}
+
+static int __init at91ether_init(void)
+{
+	if (at91ether_probe()) {
+		printk(KERN_NOTICE "at91_ether: PHY not detected.\n");
+		return -1;
+	}
+	
+	return 0;
+}
+
+static void __exit at91ether_exit(void)
+{
+	struct at91_private *lp = (struct at91_private *) at91_dev->priv;
+
+	unregister_netdev(at91_dev);
+	free_netdev(at91_dev);
+
+	free_irq(at91_dev->irq, at91_dev);
+	free_netdev(at91_dev);
+	dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
+
+	at91_dev = NULL;
+}
+
+module_init(at91ether_init)
+module_exit(at91ether_exit)
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
+MODULE_AUTHOR("Andrew Victor");
diff -urN linux-2.6.11-rc5.orig/drivers/net/arm/at91_ether.h linux-2.6.11-rc5/drivers/net/arm/at91_ether.h
--- linux-2.6.11-rc5.orig/drivers/net/arm/at91_ether.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/net/arm/at91_ether.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,89 @@
+/*
+ * Ethernet driver for the Atmel AT91RM9200 (Thunder)
+ *
+ * (c) SAN People (Pty) Ltd
+ *
+ * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
+ * Initial version by Rick Bronson.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef AT91_ETHERNET
+#define AT91_ETHERNET
+
+
+/* Davicom 9161 PHY */
+#define MII_DM9161_ID   0x0181b880
+
+/* Davicom specific registers */
+#define MII_DSCR_REG	16
+#define MII_DSCSR_REG   17
+#define MII_DSINTR_REG  21
+
+/* Intel LXT971A PHY */
+#define MII_LXT971A_ID	0x001378E0
+
+/* Intel specific registers */
+#define MII_ISINTE_REG	18
+#define MII_ISINTS_REG	19
+
+/* Realtek RTL8201 PHY */
+#define MII_RTL8201_ID	0x00008200
+
+/* Broadcom BCM5221 PHY */
+#define MII_BCM5221_ID	0x004061e0
+
+/* Broadcom specific registers */
+#define MII_BCMINTR_REG	26
+
+/* ........................................................................ */
+
+#define MAX_RBUFF_SZ	0x600		/* 1518 rounded up */
+#define MAX_RX_DESCR	9		/* max number of receive buffers */
+
+#define EMAC_DESC_DONE	0x00000001	/* bit for if DMA is done */
+#define EMAC_DESC_WRAP	0x00000002	/* bit for wrap */
+
+#define EMAC_BROADCAST	0x80000000	/* broadcast address */
+#define EMAC_MULTICAST	0x40000000	/* multicast address */
+#define EMAC_UNICAST	0x20000000	/* unicast address */
+
+struct rbf_t
+{
+	unsigned int addr;
+	unsigned long size;
+};
+
+struct recv_desc_bufs
+{
+	struct rbf_t descriptors[MAX_RX_DESCR];		/* must be on sizeof (rbf_t) boundary */
+	char recv_buf[MAX_RX_DESCR][MAX_RBUFF_SZ];	/* must be on long boundary */
+};
+
+struct at91_private
+{
+	struct net_device_stats stats;
+	struct mii_if_info mii;			/* ethtool support */
+
+	/* PHY */
+	unsigned long phy_type;			/* type of PHY (PHY_ID) */
+	spinlock_t lock;			/* lock for MDI interface */
+	short phy_media;			/* media interface type */
+	unsigned short phy_address;		/* 5-bit MDI address of PHY (0..31) */
+
+	/* Transmit */
+	struct sk_buff *skb;			/* holds skb until xmit interrupt completes */
+	dma_addr_t skb_physaddr;		/* phys addr from pci_map_single */
+	int skb_length;				/* saved skb length for pci_unmap_single */
+
+	/* Receive */
+	int rxBuffIndex;			/* index into receive descriptor list */
+	struct recv_desc_bufs *dlist;		/* descriptor list address */
+	struct recv_desc_bufs *dlist_phys;	/* descriptor list physical address */
+};
+
+#endif
diff -urN linux-2.6.11-rc5.orig/drivers/serial/Kconfig linux-2.6.11-rc5/drivers/serial/Kconfig
--- linux-2.6.11-rc5.orig/drivers/serial/Kconfig	Fri Feb 25 11:51:42 2005
+++ linux-2.6.11-rc5/drivers/serial/Kconfig	Fri Feb 25 11:55:46 2005
@@ -219,6 +219,24 @@
 	  your boot loader (lilo or loadlin) about how to pass options to the
 	  kernel at boot time.)
 
+
+config SERIAL_AT91
+	bool "AT91RM9200 serial port support"
+	depends on ARM && ARCH_AT91RM9200
+	select SERIAL_CORE
+	help
+	  This enables the driver for the on-chip UARTs of the AT91RM9200
+	  processor.
+
+config SERIAL_AT91_CONSOLE
+	bool "Support for console on AT91RM9200 serial port"
+	depends on SERIAL_AT91=y
+	select SERIAL_CORE_CONSOLE
+	help
+	  Say Y here if you wish to use a UART on the AT91RM9200 as the system
+	  console (the system console is the device which receives all kernel
+	  messages and warnings and which allows logins in single user mode).
+
 config SERIAL_CLPS711X
 	tristate "CLPS711X serial port support"
 	depends on ARM && ARCH_CLPS711X
diff -urN linux-2.6.11-rc5.orig/drivers/serial/Makefile linux-2.6.11-rc5/drivers/serial/Makefile
--- linux-2.6.11-rc5.orig/drivers/serial/Makefile	Fri Feb 25 11:51:42 2005
+++ linux-2.6.11-rc5/drivers/serial/Makefile	Fri Feb 25 11:56:09 2005
@@ -49,3 +49,4 @@
 obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
 obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o
 obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
+obj-$(CONFIG_SERIAL_AT91) += at91_serial.o
diff -urN linux-2.6.11-rc5.orig/drivers/serial/at91_serial.c linux-2.6.11-rc5/drivers/serial/at91_serial.c
--- linux-2.6.11-rc5.orig/drivers/serial/at91_serial.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/serial/at91_serial.c	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,885 @@
+/*
+ *  linux/drivers/char/at91_serial.c
+ *
+ *  Driver for Atmel AT91RM9200 Serial ports
+ *
+ *  Copyright (c) Rick Bronson
+ *
+ *  Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
+ *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/tty.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/tty_flip.h>
+
+#include <asm/arch/AT91RM9200_USART.h>
+#include <asm/mach/serial_at91rm9200.h>
+#include <asm/arch/pio.h>
+
+
+#if defined(CONFIG_SERIAL_AT91_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/serial_core.h>
+
+#define SERIAL_AT91_MAJOR	TTY_MAJOR
+#define CALLOUT_AT91_MAJOR	TTYAUX_MAJOR
+#define MINOR_START		64
+
+#define AT91C_VA_BASE_DBGU	((unsigned long) &(AT91_SYS->DBGU_CR))
+#define AT91_ISR_PASS_LIMIT	256
+
+#define UART_PUT_CR(port,v)	((AT91PS_USART)(port)->membase)->US_CR = v
+#define UART_GET_MR(port)	((AT91PS_USART)(port)->membase)->US_MR
+#define UART_PUT_MR(port,v)	((AT91PS_USART)(port)->membase)->US_MR = v
+#define UART_PUT_IER(port,v)	((AT91PS_USART)(port)->membase)->US_IER = v
+#define UART_PUT_IDR(port,v)	((AT91PS_USART)(port)->membase)->US_IDR = v
+#define UART_GET_IMR(port)	((AT91PS_USART)(port)->membase)->US_IMR
+#define UART_GET_CSR(port)	((AT91PS_USART)(port)->membase)->US_CSR
+#define UART_GET_CHAR(port)	((AT91PS_USART)(port)->membase)->US_RHR
+#define UART_PUT_CHAR(port,v)	((AT91PS_USART)(port)->membase)->US_THR = v
+#define UART_GET_BRGR(port)	((AT91PS_USART)(port)->membase)->US_BRGR
+#define UART_PUT_BRGR(port,v)	((AT91PS_USART)(port)->membase)->US_BRGR = v
+#define UART_PUT_RTOR(port,v)	((AT91PS_USART)(port)->membase)->US_RTOR = v
+
+// #define UART_GET_CR(port)	((AT91PS_USART)(port)->membase)->US_CR		// is write-only
+
+ /* PDC registers */
+#define UART_PUT_PTCR(port,v)	((AT91PS_USART)(port)->membase)->US_PTCR = v
+#define UART_PUT_RPR(port,v)	((AT91PS_USART)(port)->membase)->US_RPR = v
+#define UART_PUT_RCR(port,v)	((AT91PS_USART)(port)->membase)->US_RCR = v
+#define UART_GET_RCR(port)	((AT91PS_USART)(port)->membase)->US_RCR
+#define UART_PUT_RNPR(port,v)	((AT91PS_USART)(port)->membase)->US_RNPR = v
+#define UART_PUT_RNCR(port,v)	((AT91PS_USART)(port)->membase)->US_RNCR = v
+
+
+const int at91_serialmap[AT91C_NR_UART] = AT91C_UART_MAP;
+
+static int (*at91_open)(struct uart_port *);
+static void (*at91_close)(struct uart_port *);
+
+#ifdef SUPPORT_SYSRQ
+static struct console at91_console;
+#endif
+
+/*
+ * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
+ */
+static u_int at91_tx_empty(struct uart_port *port)
+{
+	return (UART_GET_CSR(port) & AT91C_US_TXEMPTY) ? TIOCSER_TEMT : 0;
+}
+
+/*
+ * Set state of the modem control output lines
+ */
+static void at91_set_mctrl(struct uart_port *port, u_int mctrl)
+{
+	unsigned int control = 0;
+
+	/*
+	 * Errata #39: RTS0 is not internally connected to PA21.  We need to drive
+	 *  the pin manually.
+	 */
+	if (port->mapbase == AT91C_VA_BASE_US0) {
+		if (mctrl & TIOCM_RTS)
+			AT91_SYS->PIOA_CODR = AT91C_PA21_RTS0;
+		else
+			AT91_SYS->PIOA_SODR = AT91C_PA21_RTS0;
+	}
+
+	if (mctrl & TIOCM_RTS)
+		control |= AT91C_US_RTSEN;
+	else
+		control |= AT91C_US_RTSDIS;
+
+	if (mctrl & TIOCM_DTR)
+		control |= AT91C_US_DTREN;
+	else
+		control |=  AT91C_US_DTRDIS;
+
+	UART_PUT_CR(port,control);
+}
+
+/*
+ * Get state of the modem control input lines
+ */
+static u_int at91_get_mctrl(struct uart_port *port)
+{
+	unsigned int status, ret = 0;
+
+	status = UART_GET_CSR(port);
+	if (status & AT91C_US_DCD)
+		ret |= TIOCM_CD;
+	if (status & AT91C_US_CTS)
+		ret |= TIOCM_CTS;
+	if (status & AT91C_US_DSR)
+		ret |= TIOCM_DSR;
+	if (status & AT91C_US_RI)
+		ret |= TIOCM_RI;
+
+	return ret;
+}
+
+/*
+ * Stop transmitting.
+ */
+static void at91_stop_tx(struct uart_port *port, u_int from_tty)
+{
+	UART_PUT_IDR(port, AT91C_US_TXRDY);
+	port->read_status_mask &= ~AT91C_US_TXRDY;
+}
+
+/*
+ * Start transmitting.
+ */
+static void at91_start_tx(struct uart_port *port, u_int from_tty)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	port->read_status_mask |= AT91C_US_TXRDY;
+	UART_PUT_IER(port, AT91C_US_TXRDY);
+	local_irq_restore(flags);
+
+}
+
+/*
+ * Stop receiving - port is in process of being closed.
+ */
+static void at91_stop_rx(struct uart_port *port)
+{
+	UART_PUT_IDR(port, AT91C_US_RXRDY);
+}
+
+/*
+ * Enable modem status interrupts
+ */
+static void at91_enable_ms(struct uart_port *port)
+{
+	UART_PUT_IER(port, AT91C_US_RIIC | AT91C_US_DSRIC | AT91C_US_DCDIC | AT91C_US_CTSIC);
+}
+
+/*
+ * Control the transmission of a break signal
+ */
+static void at91_break_ctl(struct uart_port *port, int break_state)
+{
+	if (break_state != 0)
+		UART_PUT_CR(port, AT91C_US_STTBRK);	/* start break */
+	else
+		UART_PUT_CR(port, AT91C_US_STPBRK);	/* stop break */
+}
+
+/*
+ * Characters received (called from interrupt handler)
+ */
+static void at91_rx_chars(struct uart_port *port, struct pt_regs *regs)
+{
+	struct tty_struct *tty = port->info->tty;
+	unsigned int status, ch, flg, ignored = 0;
+
+	status = UART_GET_CSR(port) & port->read_status_mask;
+	while (status & (AT91C_US_RXRDY)) {
+		ch = UART_GET_CHAR(port);
+
+		if (tty->flip.count >= TTY_FLIPBUF_SIZE)
+			goto ignore_char;
+		port->icount.rx++;
+
+		flg = TTY_NORMAL;
+
+		/*
+		 * note that the error handling code is
+		 * out of the main execution path
+		 */
+		if (status & (AT91C_US_PARE | AT91C_US_FRAME | AT91C_US_OVRE))
+			goto handle_error;
+
+		if (uart_handle_sysrq_char(port, ch, regs))
+			goto ignore_char;
+
+	error_return:
+		tty_insert_flip_char(tty, ch, flg);
+	ignore_char:
+		status = UART_GET_CSR(port) & port->read_status_mask;
+	}
+out:
+	tty_flip_buffer_push(tty);
+	return;
+
+handle_error:
+	if (status & (AT91C_US_PARE | AT91C_US_FRAME | AT91C_US_OVRE))
+		UART_PUT_CR(port, AT91C_US_RSTSTA);  /* clear error */
+	if (status & (AT91C_US_PARE))
+		port->icount.parity++;
+	else if (status & (AT91C_US_FRAME))
+		port->icount.frame++;
+	if (status & (AT91C_US_OVRE))
+		port->icount.overrun++;
+
+	if (status & port->ignore_status_mask) {
+		if (++ignored > 100)
+			goto out;
+		goto ignore_char;
+	}
+
+	status &= port->read_status_mask;
+
+	UART_PUT_CR(port, AT91C_US_RSTSTA);  /* clear error */
+	if (status & AT91C_US_PARE)
+		flg = TTY_PARITY;
+	else if (status & AT91C_US_FRAME)
+		flg = TTY_FRAME;
+
+	if (status & AT91C_US_OVRE) {
+		/*
+		 * overrun does *not* affect the character
+		 * we read from the FIFO
+		 */
+		tty_insert_flip_char(tty, ch, flg);
+		ch = 0;
+		flg = TTY_OVERRUN;
+	}
+#ifdef SUPPORT_SYSRQ
+	port->sysrq = 0;
+#endif
+	goto error_return;
+}
+
+/*
+ * Transmit characters (called from interrupt handler)
+ */
+static void at91_tx_chars(struct uart_port *port)
+{
+	struct circ_buf *xmit = &port->info->xmit;
+
+	if (port->x_char) {
+		UART_PUT_CHAR(port, port->x_char);
+		port->icount.tx++;
+		port->x_char = 0;
+		return;
+	}
+	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+		at91_stop_tx(port, 0);
+		return;
+	}
+
+	while (UART_GET_CSR(port) & AT91C_US_TXRDY) {
+		UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		port->icount.tx++;
+		if (uart_circ_empty(xmit))
+			break;
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+
+	if (uart_circ_empty(xmit))
+		at91_stop_tx(port, 0);
+}
+
+/*
+ * Interrupt handler
+ */
+static irqreturn_t at91_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	struct uart_port *port = dev_id;
+	unsigned int status, pending, pass_counter = 0;
+
+	status = UART_GET_CSR(port);
+	pending = status & port->read_status_mask;
+	if (pending) {
+		do {
+			if (pending & AT91C_US_RXRDY)
+				at91_rx_chars(port, regs);
+
+			/* Clear the relevent break bits */
+			if (pending & AT91C_US_RXBRK) {
+				UART_PUT_CR(port, AT91C_US_RSTSTA);
+				port->icount.brk++;
+				uart_handle_break(port);
+			}
+
+			// TODO: All reads to CSR will clear these interrupts!
+			if (pending & AT91C_US_RIIC) port->icount.rng++;
+			if (pending & AT91C_US_DSRIC) port->icount.dsr++;
+			if (pending & AT91C_US_DCDIC) {
+				port->icount.dcd++;
+				uart_handle_dcd_change(port, status & AT91C_US_DCD);
+			}
+			if (pending & AT91C_US_CTSIC) {
+				port->icount.cts++;
+				uart_handle_cts_change(port, status & AT91C_US_CTS);
+			}
+			if (pending & (AT91C_US_RIIC | AT91C_US_DSRIC | AT91C_US_DCDIC | AT91C_US_CTSIC))
+				wake_up_interruptible(&port->info->delta_msr_wait);
+
+			if (pending & AT91C_US_TXRDY)
+				at91_tx_chars(port);
+			if (pass_counter++ > AT91_ISR_PASS_LIMIT)
+				break;
+
+			status = UART_GET_CSR(port);
+			pending = status & port->read_status_mask;
+		} while (pending);
+	}
+	return IRQ_HANDLED;
+}
+
+/*
+ * Perform initialization and enable port for reception
+ */
+static int at91_startup(struct uart_port *port)
+{
+	int retval;
+
+	/*
+	 * Allocate the IRQ
+	 */
+	retval = request_irq(port->irq, at91_interrupt, SA_SHIRQ, "at91_serial", port);
+	if (retval) {
+		printk("at91_serial: at91_startup - Can't get irq\n");
+		return retval;
+	}
+	/*
+	 * If there is a specific "open" function (to register
+	 * control line interrupts)
+	 */
+	if (at91_open) {
+		retval = at91_open(port);
+		if (retval) {
+			free_irq(port->irq, port);
+			return retval;
+		}
+	}
+
+	port->read_status_mask = AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_OVRE
+			| AT91C_US_FRAME | AT91C_US_PARE | AT91C_US_RXBRK;
+	/*
+	 * Finally, clear and enable interrupts
+	 */
+	UART_PUT_IDR(port, -1);
+	UART_PUT_CR(port, AT91C_US_TXEN | AT91C_US_RXEN);  /* enable xmit & rcvr */
+	UART_PUT_IER(port, AT91C_US_RXRDY);  /* do receive only */
+	return 0;
+}
+
+/*
+ * Disable the port
+ */
+static void at91_shutdown(struct uart_port *port)
+{
+	/*
+	 * Free the interrupt
+	 */
+	free_irq(port->irq, port);
+
+	/*
+	 * If there is a specific "close" function (to unregister
+	 * control line interrupts)
+	 */
+	if (at91_close)
+		at91_close(port);
+
+	/*
+	 * Disable all interrupts, port and break condition.
+	 */
+	UART_PUT_CR(port, AT91C_US_RSTSTA);
+	UART_PUT_IDR(port, -1);
+}
+
+/*
+ * Power / Clock management.
+ */
+static void at91_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
+{
+	switch (state) {
+		case 0:
+			/*
+			 * Enable the peripheral clock for this serial port.
+			 * This is called on uart_open() or a resume event.
+			 */
+			AT91_SYS->PMC_PCER = 1 << port->irq;
+			break;
+		case 3:
+			/*
+			 * Disable the peripheral clock for this serial port.
+			 * This is called on uart_close() or a suspend event.
+			 */
+			if (port->irq != AT91C_ID_SYS)			/* is this a shared clock? */
+				AT91_SYS->PMC_PCDR = 1 << port->irq;
+			break;
+		default:
+			printk(KERN_ERR "at91_serial: unknown pm %d\n", state);
+	}
+}
+
+static struct uart_ops at91_pops;		/* forward declaration */
+
+/*
+ * Change the port parameters
+ */
+static void at91_set_termios(struct uart_port *port, struct termios * termios, struct termios * old)
+{
+	unsigned long flags;
+	unsigned int mode, imr, quot, baud;
+	
+
+	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 
+	quot = uart_get_divisor(port, baud);
+
+	/* Get current mode register */
+	mode = UART_GET_MR(port) & ~(AT91C_US_CHRL | AT91C_US_NBSTOP | AT91C_US_PAR);
+
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	/* byte size */
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:
+		mode |= AT91C_US_CHRL_5_BITS;
+		break;
+	case CS6:
+		mode |= AT91C_US_CHRL_6_BITS;
+		break;
+	case CS7:
+		mode |= AT91C_US_CHRL_7_BITS;
+		break;
+	default:
+		mode |= AT91C_US_CHRL_8_BITS;
+		break;
+	}
+
+	/* stop bits */
+	if (termios->c_cflag & CSTOPB)
+		mode |= AT91C_US_NBSTOP_2_BIT;
+
+	/* parity */
+	if (termios->c_cflag & PARENB) {
+		if (termios->c_cflag & CMSPAR) {			/* Mark or Space parity */
+			if (termios->c_cflag & PARODD)
+				mode |= AT91C_US_PAR_MARK;
+			else
+				mode |= AT91C_US_PAR_SPACE;
+		}
+		else if (termios->c_cflag & PARODD)
+			mode |= AT91C_US_PAR_ODD;
+		else
+			mode |= AT91C_US_PAR_EVEN;
+	}
+	else
+		mode |= AT91C_US_PAR_NONE;
+
+	port->read_status_mask |= AT91C_US_OVRE;
+	if (termios->c_iflag & INPCK)
+		port->read_status_mask |= AT91C_US_FRAME | AT91C_US_PARE;
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		port->read_status_mask |= AT91C_US_RXBRK;
+
+	/*
+	 * Characters to ignore
+	 */
+	port->ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		port->ignore_status_mask |= (AT91C_US_FRAME | AT91C_US_PARE);
+	if (termios->c_iflag & IGNBRK) {
+		port->ignore_status_mask |= AT91C_US_RXBRK;
+		/*
+		 * If we're ignoring parity and break indicators,
+		 * ignore overruns too (for real raw support).
+		 */
+		if (termios->c_iflag & IGNPAR)
+			port->ignore_status_mask |= AT91C_US_OVRE;
+	}
+
+	// TODO: Ignore all characters if CREAD is set.
+
+	/* first, disable interrupts and drain transmitter */
+	local_irq_save(flags);
+	imr = UART_GET_IMR(port);	/* get interrupt mask */
+	UART_PUT_IDR(port, -1);		/* disable all interrupts */
+	local_irq_restore(flags);
+	while (!(UART_GET_CSR(port) & AT91C_US_TXEMPTY)) { barrier(); }
+
+	/* disable receiver and transmitter */
+	UART_PUT_CR(port, AT91C_US_TXDIS | AT91C_US_RXDIS);
+
+	/* set the parity, stop bits and data size */
+	UART_PUT_MR(port, mode);
+
+	/* set the baud rate */
+	UART_PUT_BRGR(port, quot);
+	UART_PUT_CR(port, AT91C_US_TXEN | AT91C_US_RXEN);
+
+	/* restore interrupts */
+	UART_PUT_IER(port, imr);
+
+	/* CTS flow-control and modem-status interrupts */
+	if (UART_ENABLE_MS(port, termios->c_cflag))
+		at91_pops.enable_ms(port);
+}
+
+/*
+ * Return string describing the specified port
+ */
+static const char *at91_type(struct uart_port *port)
+{
+	return (port->type == PORT_AT91RM9200) ? "AT91_SERIAL" : NULL;
+}
+
+/*
+ * Release the memory region(s) being used by 'port'.
+ */
+static void at91_release_port(struct uart_port *port)
+{
+	release_mem_region(port->mapbase,
+		(port->mapbase == AT91C_VA_BASE_DBGU) ? 512 : SZ_16K);
+}
+
+/*
+ * Request the memory region(s) being used by 'port'.
+ */
+static int at91_request_port(struct uart_port *port)
+{
+	return request_mem_region(port->mapbase,
+		(port->mapbase == AT91C_VA_BASE_DBGU) ? 512 : SZ_16K,
+		"at91_serial") != NULL ? 0 : -EBUSY;
+
+}
+
+/*
+ * Configure/autoconfigure the port.
+ */
+static void at91_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE) {
+		port->type = PORT_AT91RM9200;
+		at91_request_port(port);
+	}
+}
+
+/*
+ * Verify the new serial_struct (for TIOCSSERIAL).
+ */
+static int at91_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+	int ret = 0;
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_AT91RM9200)
+		ret = -EINVAL;
+	if (port->irq != ser->irq)
+		ret = -EINVAL;
+	if (ser->io_type != SERIAL_IO_MEM)
+		ret = -EINVAL;
+	if (port->uartclk / 16 != ser->baud_base)
+		ret = -EINVAL;
+	if ((void *)port->mapbase != ser->iomem_base)
+		ret = -EINVAL;
+	if (port->iobase != ser->port)
+		ret = -EINVAL;
+	if (ser->hub6 != 0)
+		ret = -EINVAL;
+	return ret;
+}
+
+static struct uart_ops at91_pops = {
+	.tx_empty	= at91_tx_empty,
+	.set_mctrl	= at91_set_mctrl,
+	.get_mctrl	= at91_get_mctrl,
+	.stop_tx	= at91_stop_tx,
+	.start_tx	= at91_start_tx,
+	.stop_rx	= at91_stop_rx,
+	.enable_ms	= at91_enable_ms,
+	.break_ctl	= at91_break_ctl,
+	.startup	= at91_startup,
+	.shutdown	= at91_shutdown,
+	.set_termios	= at91_set_termios,
+	.type		= at91_type,
+	.release_port	= at91_release_port,
+	.request_port	= at91_request_port,
+	.config_port 	= at91_config_port,
+	.verify_port 	= at91_verify_port,
+	.pm		= at91_serial_pm,
+};
+
+static struct uart_port at91_ports[AT91C_NR_UART];
+
+void __init at91_init_ports(void)
+{
+	static int first = 1;
+	int i;
+
+	if (!first)
+		return;
+	first = 0;
+
+	for (i = 0; i < AT91C_NR_UART; i++) {
+		at91_ports[i].iotype	= SERIAL_IO_MEM;
+		at91_ports[i].flags     = ASYNC_BOOT_AUTOCONF;
+		at91_ports[i].uartclk   = AT91C_MASTER_CLOCK;
+		at91_ports[i].ops	= &at91_pops;
+		at91_ports[i].fifosize  = 1;
+		at91_ports[i].line	= i;
+ 	}
+}
+
+void __init at91_register_uart_fns(struct at91rm9200_port_fns *fns)
+{
+	if (fns->enable_ms)
+		at91_pops.enable_ms = fns->enable_ms;
+	if (fns->get_mctrl)
+		at91_pops.get_mctrl = fns->get_mctrl;
+	if (fns->set_mctrl)
+		at91_pops.set_mctrl = fns->set_mctrl;
+	at91_open          = fns->open;
+	at91_close         = fns->close;
+	at91_pops.pm       = fns->pm;
+	at91_pops.set_wake = fns->set_wake;
+}
+
+/*
+ * Setup ports.
+ */
+void __init at91_register_uart(int idx, int port)
+{
+	if ((idx < 0) || (idx >= AT91C_NR_UART)) {
+		printk(KERN_ERR "%s: bad index number %d\n", __FUNCTION__, idx);
+		return;
+	}
+
+	switch (port) {
+	case 0:
+		at91_ports[idx].membase = (void *) AT91C_VA_BASE_US0;
+		at91_ports[idx].mapbase = AT91C_VA_BASE_US0;
+		at91_ports[idx].irq     = AT91C_ID_US0;
+		AT91_CfgPIO_USART0();
+		break;
+	case 1:
+		at91_ports[idx].membase = (void *) AT91C_VA_BASE_US1;
+		at91_ports[idx].mapbase = AT91C_VA_BASE_US1;
+		at91_ports[idx].irq     = AT91C_ID_US1;
+		AT91_CfgPIO_USART1();
+		break;
+	case 2:
+		at91_ports[idx].membase = (void *) AT91C_VA_BASE_US2;
+		at91_ports[idx].mapbase = AT91C_VA_BASE_US2;
+		at91_ports[idx].irq     = AT91C_ID_US2;
+		AT91_CfgPIO_USART2();
+		break;
+	case 3:
+		at91_ports[idx].membase = (void *) AT91C_VA_BASE_US3;
+		at91_ports[idx].mapbase = AT91C_VA_BASE_US3;
+		at91_ports[idx].irq     = AT91C_ID_US3;
+		AT91_CfgPIO_USART3();
+		break;
+	case 4:
+		at91_ports[idx].membase = (void *) AT91C_VA_BASE_DBGU;
+		at91_ports[idx].mapbase = AT91C_VA_BASE_DBGU;
+		at91_ports[idx].irq     = AT91C_ID_SYS;
+		AT91_CfgPIO_DBGU();
+		break;
+	default:
+		printk(KERN_ERR  "%s : bad port number %d\n", __FUNCTION__, port);
+	}
+}
+
+#ifdef CONFIG_SERIAL_AT91_CONSOLE
+
+/*
+ * Interrupts are disabled on entering
+ */
+static void at91_console_write(struct console *co, const char *s, u_int count)
+{
+	struct uart_port *port = at91_ports + co->index;
+	unsigned int status, i, imr;
+
+	/*
+	 *	First, save IMR and then disable interrupts
+	 */
+	imr = UART_GET_IMR(port);	/* get interrupt mask */
+	UART_PUT_IDR(port, AT91C_US_RXRDY | AT91C_US_TXRDY);
+
+	/*
+	 *	Now, do each character
+	 */
+	for (i = 0; i < count; i++) {
+		do {
+			status = UART_GET_CSR(port);
+		} while (!(status & AT91C_US_TXRDY));
+		UART_PUT_CHAR(port, s[i]);
+		if (s[i] == '\n') {
+			do {
+				status = UART_GET_CSR(port);
+			} while (!(status & AT91C_US_TXRDY));
+			UART_PUT_CHAR(port, '\r');
+		}
+	}
+
+	/*
+	 *	Finally, wait for transmitter to become empty
+	 *	and restore IMR
+	 */
+	do {
+		status = UART_GET_CSR(port);
+	} while (!(status & AT91C_US_TXRDY));
+	UART_PUT_IER(port, imr);	/* set interrupts back the way they were */
+}
+
+/*
+ * If the port was already initialised (eg, by a boot loader), try to determine
+ * the current setup.
+ */
+static void __init at91_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
+{
+	unsigned int mr, quot;
+
+// TODO: CR is a write-only register
+//	unsigned int cr;
+//
+//	cr = UART_GET_CR(port) & (AT91C_US_RXEN | AT91C_US_TXEN);
+//	if (cr == (AT91C_US_RXEN | AT91C_US_TXEN)) {
+//		/* ok, the port was enabled */
+//
+//		mr = UART_GET_MR(port) & AT91C_US_PAR;
+//
+//		*parity = 'n';
+//		if (mr == AT91C_US_PAR_EVEN)
+//			*parity = 'e';
+//		else if (mr == AT91C_US_PAR_ODD)
+//			*parity = 'o';
+//	}
+
+	mr = UART_GET_MR(port) & AT91C_US_CHRL;
+	if (mr == AT91C_US_CHRL_8_BITS)
+		*bits = 8;
+	else
+		*bits = 7;
+
+	quot = UART_GET_BRGR(port);
+	*baud = port->uartclk / (16 * (quot));
+}
+
+static int __init at91_console_setup(struct console *co, char *options)
+{
+	struct uart_port *port;
+	int baud = AT91C_CONSOLE_DEFAULT_BAUDRATE;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	/*
+	 * Check whether an invalid uart number has been specified, and
+	 * if so, search for the first available port that does have
+	 * console support.
+	 */
+	port = uart_get_console(at91_ports, AT91C_NR_UART, co);
+
+	/*
+	 * Enable the serial console, in-case bootloader did not do it.
+	 */
+	AT91_SYS->PMC_PCER = 1 << port->irq;		/* enable clock */
+	UART_PUT_IDR(port, -1);				/* disable interrupts */
+	
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	else
+		at91_console_get_options(port, &baud, &parity, &bits);
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+extern struct uart_driver at91_uart;
+
+static struct console at91_console = {
+	.name		= "ttyS",
+	.write		= at91_console_write,
+	.device		= uart_console_device,
+	.setup		= at91_console_setup,
+	.flags		= CON_PRINTBUFFER,
+	.index		= AT91C_CONSOLE,
+	.data		= &at91_uart,
+};
+
+#define AT91_CONSOLE_DEVICE	&at91_console
+
+static int  __init at91_console_init(void)
+{
+	at91_init_ports();
+	register_console(&at91_console);
+	return 0;
+}
+console_initcall(at91_console_init);
+
+#else
+#define AT91_CONSOLE_DEVICE	NULL
+#endif
+
+static struct uart_driver at91_uart = {
+	.driver_name		= "ttyS",
+	.dev_name		= "ttyS",
+	.devfs_name		= "ttyS",
+	.major			= SERIAL_AT91_MAJOR,
+	.minor			= MINOR_START,
+	.nr			= AT91C_NR_UART,
+	.cons			= AT91_CONSOLE_DEVICE,
+};
+
+static int __init at91_serial_init(void)
+{
+	int ret, i;
+
+	at91_init_ports();
+
+	ret = uart_register_driver(&at91_uart);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < AT91C_NR_UART; i++) {
+		if (at91_serialmap[i] >= 0)
+			uart_add_one_port(&at91_uart, &at91_ports[i]);
+	}
+
+	return 0;
+}
+
+static void __exit at91_serial_exit(void)
+{
+	int i;
+
+	for (i = 0; i < AT91C_NR_UART; i++) {
+ 		if (at91_serialmap[i] >= 0)
+			uart_remove_one_port(&at91_uart, &at91_ports[i]);
+  	}
+
+	uart_unregister_driver(&at91_uart);
+}
+
+module_init(at91_serial_init);
+module_exit(at91_serial_exit);
+
+MODULE_AUTHOR("Rick Bronson");
+MODULE_DESCRIPTION("AT91 generic serial port driver");
+MODULE_LICENSE("GPL");
diff -urN linux-2.6.11-rc5.orig/drivers/usb/Makefile linux-2.6.11-rc5/drivers/usb/Makefile
--- linux-2.6.11-rc5.orig/drivers/usb/Makefile	Fri Feb 25 11:51:43 2005
+++ linux-2.6.11-rc5/drivers/usb/Makefile	Fri Feb 25 11:55:46 2005
@@ -11,6 +11,7 @@
 obj-$(CONFIG_USB_UHCI_HCD)	+= host/
 obj-$(CONFIG_USB_SL811_HCD)	+= host/
 obj-$(CONFIG_ETRAX_USB_HOST)	+= host/
+obj-$(CONFIG_USB_OHCI_AT91)	+= host/
 
 obj-$(CONFIG_USB_ACM)		+= class/
 obj-$(CONFIG_USB_AUDIO)		+= class/
diff -urN linux-2.6.11-rc5.orig/drivers/usb/host/Kconfig linux-2.6.11-rc5/drivers/usb/host/Kconfig
--- linux-2.6.11-rc5.orig/drivers/usb/host/Kconfig	Fri Feb 25 11:50:47 2005
+++ linux-2.6.11-rc5/drivers/usb/host/Kconfig	Fri Feb 25 11:55:46 2005
@@ -14,6 +14,7 @@
 	default y if ARCH_OMAP
 	default y if ARCH_LH7A404
 	default y if PXA27x
+	default y if ARCH_AT91RM9200
 	default PCI
 
 #
diff -urN linux-2.6.11-rc5.orig/drivers/usb/host/ohci-at91.c linux-2.6.11-rc5/drivers/usb/host/ohci-at91.c
--- linux-2.6.11-rc5.orig/drivers/usb/host/ohci-at91.c	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/drivers/usb/host/ohci-at91.c	Fri Feb 25 12:22:23 2005
@@ -0,0 +1,348 @@
+/*
+ * OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 2004 SAN People (Pty) Ltd.
+ * (C) Copyright 2005 Thibaut VARENE <varenet@parisc-linux.org>
+ * 
+ * AT91RM9200 Bus Glue
+ *
+ * Based on fragments of 2,4 driver by Rick Bronson.
+ * Based on ohci-omap.c
+ *
+ * This file is licenced under the GPL.
+ */
+
+#include <linux/device.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/arch/AT91RM9200_UHP.h>
+
+#ifndef CONFIG_ARCH_AT91RM9200
+#error "This file is AT91RM9200 bus glue.  CONFIG_ARCH_AT91RM9200 must be defined."
+#endif
+
+AT91PS_UHP __iomem ohci_regs;
+
+extern int usb_disabled(void);
+
+/*-------------------------------------------------------------------------*/
+
+static void at91_start_hc(struct platform_device *pdev)
+{
+	dev_dbg(&pdev->dev, "starting AT91RM9200 OHCI USB Controller\n");
+
+	/* Enable PLLB */
+	AT91_SYS->CKGR_PLLBR = AT91_PLLB_INIT;
+	while ((AT91_SYS->PMC_SR & 4) == 0);
+
+	/*
+	 * Configure the power sense and control lines.  Place the USB
+	 * host controller in reset.
+	 */
+	ohci_regs->UHP_HcControl = 0;
+	 
+	/* Enable the USB clock */
+	AT91_SYS->PMC_SCER = AT91C_PMC_UHP;	/* enable system clock */
+	AT91_SYS->PMC_PCER = 1 << AT91C_ID_UHP; /* enable peripheral clock */
+	
+	/* Take Hc out of reset */
+	ohci_regs->UHP_HcControl = 2 << 6;	/* HCFS: '10b' -> USBOperational */
+}
+
+static void at91_stop_hc(struct platform_device *pdev)
+{
+	dev_dbg(&pdev->dev, "stopping AT91RM9200 OHCI USB Controller\n");
+
+	/*
+	 * Put the USB host controller into reset.
+	 */
+	ohci_regs->UHP_HcControl = 0;
+
+	/*
+	 * Stop the USB clock.
+	 */
+	AT91_SYS->PMC_SCDR = AT91C_PMC_UHP;     /* disable system clock */
+	AT91_SYS->PMC_PCDR = 1 << AT91C_ID_UHP; /* disable peripheral clock */
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+void usb_hcd_at91_remove (struct usb_hcd *, struct platform_device *);
+
+/* configure so an HC device and id are always provided */
+/* always called with process context; sleeping is OK */
+
+
+/**
+ * usb_hcd_at91_probe - initialize AT91RM9200-based HCDs
+ * Context: !in_interrupt()
+ *
+ * Allocates basic resources for this USB host controller, and
+ * then invokes the start() method for the HCD associated with it
+ * through the hotplug entry's driver_data.
+ *
+ * Store this function in the HCD's struct pci_driver as probe().
+ */
+int usb_hcd_at91_probe (const struct hc_driver *driver,
+			struct platform_device *pdev)
+{
+	int retval;
+	struct usb_hcd *hcd = NULL;
+
+	if (pdev->num_resources != 1) {
+		dev_err(&pdev->dev, "hcd probe: invalid num_resources: %i\n", 
+		       pdev->num_resources);
+		return -ENODEV;
+	}
+
+	if (pdev->resource[0].flags != IORESOURCE_MEM) {
+		dev_err(&pdev->dev, "hcd probe: invalid resource type\n");
+		return -ENODEV;
+	}
+
+	if (!request_mem_region(pdev->resource[0].start, 
+				pdev->resource[0].end - pdev->resource[0].start, hcd_name)) {
+		dev_dbg(&pdev->dev, "request_mem_region failed\n");
+		return -EBUSY;
+	}
+	
+	ohci_regs = ioremap(pdev->resource[0].start, 
+				pdev->resource[0].end - pdev->resource[0].start);
+	if (!ohci_regs) {
+		dev_err(&pdev->dev, "%s(%s:%d): ioremap failed\n",
+			__func__, __FILE__, __LINE__);
+		return -EIO;
+	}
+
+	hcd = usb_create_hcd(driver);
+	if (hcd == NULL) {
+		dev_err(&pdev->dev, "hcd_alloc failed\n");
+		retval = -ENOMEM;
+		goto err1;
+	}
+	dev_set_drvdata(&pdev->dev, hcd);
+	ohci_hcd_init(hcd_to_ohci(hcd));
+
+	hcd->irq = AT91C_ID_UHP;
+	hcd->regs = ohci_regs;
+	hcd->self.controller = &pdev->dev;
+
+	at91_start_hc(pdev);
+	
+	retval = hcd_buffer_create(hcd);
+	if (retval != 0) {
+		dev_dbg(&pdev->dev, "pool alloc fail");
+		goto err2;
+	}
+
+	retval = request_irq(hcd->irq, usb_hcd_irq, SA_INTERRUPT,
+			      hcd->driver->description, hcd);
+	if (retval != 0) {
+		dev_dbg(&pdev->dev, "request_irq failed");
+		retval = -EBUSY;
+		goto err3;
+	}
+
+	printk(KERN_INFO "%s (AT91RM9200) at 0x%p, irq %d\n",
+		hcd->driver->description, (void *)pdev->resource[0].start, hcd->irq);
+
+	hcd->self.bus_name = pdev->dev.bus_id;
+	hcd->product_desc = "AT91RM9200 OHCI";
+
+	usb_register_bus(&hcd->self);
+
+	if ((retval = driver->start (hcd)) < 0) {
+		usb_hcd_at91_remove(hcd, pdev);
+		dev_dbg(&pdev->dev, "driver start failed");
+		return retval;
+	}
+	return 0;
+
+ err3:
+	hcd_buffer_destroy(hcd);
+ err2:
+	dev_set_drvdata(&pdev->dev, NULL);
+ 	usb_put_hcd(hcd);
+ err1:
+	at91_stop_hc(pdev);
+	iounmap(ohci_regs);
+ 	release_mem_region(pdev->resource[0].start, 
+			   pdev->resource[0].end - pdev->resource[0].start);
+	
+	return retval;
+}
+
+
+/* may be called without controller electrically present */
+/* may be called with controller, bus, and devices active */
+
+/**
+ * usb_hcd_at91_remove - shutdown processing for AT91RM9200-based HCDs
+ * @dev: USB Host Controller being removed
+ * Context: !in_interrupt()
+ *
+ * Reverses the effect of usb_hcd_at91_probe(), first invoking
+ * the HCD's stop() method.  It is always called from a thread
+ * context, normally "rmmod", "apmd", or something similar.
+ *
+ */
+void usb_hcd_at91_remove (struct usb_hcd *hcd, struct platform_device *pdev)
+{
+	dev_info(&pdev->dev, "remove: %s, state %x", hcd->self.bus_name, hcd->state);
+
+	if (unlikely(in_interrupt()))
+		BUG ();
+
+	hcd->state = USB_STATE_QUIESCING;
+
+	dev_dbg(&pdev->dev, "%s: roothub graceful disconnect", hcd->self.bus_name);
+	usb_disconnect (&hcd->self.root_hub);
+
+	hcd->driver->stop(hcd);
+	hcd_buffer_destroy(hcd);
+	hcd->state = USB_STATE_HALT;
+
+	free_irq(hcd->irq, hcd);
+
+	usb_deregister_bus(&hcd->self);
+
+	at91_stop_hc(pdev);
+	
+	iounmap(ohci_regs);
+ 	release_mem_region(pdev->resource[0].start, 
+			   pdev->resource[0].end - pdev->resource[0].start);	
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int __devinit
+ohci_at91_start (struct usb_hcd *hcd)
+{
+	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
+	int		ret;
+	
+	if ((ret = ohci_init(ohci)) < 0)
+		return ret;
+
+	if ((ret = ohci_run(ohci)) < 0) {
+		err("can't start %s", hcd->self.bus_name);
+		ohci_stop(hcd);
+		return ret;
+	}
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static const struct hc_driver ohci_at91_hc_driver = {
+	.description =		hcd_name,
+	.product_desc =		"AT91RM9200 OHCI",
+	.hcd_priv_size =	sizeof(struct ohci_hcd),
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq =			ohci_irq,
+	.flags =		HCD_USB11,
+
+	/*
+	 * basic lifecycle operations
+	 */
+	.start =		ohci_at91_start,
+	.stop =			ohci_stop,
+
+#if defined(CONFIG_PM)
+	/* suspend:		ohci_at91_suspend,  -- tbd TODO: */
+	/* resume:		ohci_at91_resume,   -- tbd TODO: */
+#endif
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue =		ohci_urb_enqueue,
+	.urb_dequeue =		ohci_urb_dequeue,
+	.endpoint_disable =	ohci_endpoint_disable,
+
+	/*
+	 * scheduling support
+	 */
+	.get_frame_number =	ohci_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_status_data =	ohci_hub_status_data,
+	.hub_control =		ohci_hub_control,
+
+#if defined(CONFIG_USB_SUSPEND)
+	.hub_suspend =		ohci_hub_suspend,
+	.hub_resume =		ohci_hub_resume,
+#endif
+	.start_port_reset =	ohci_start_port_reset,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int ohci_hcd_at91_drv_probe(struct device *dev)
+{
+	return usb_hcd_at91_probe(&ohci_at91_hc_driver, to_platform_device(dev));
+}
+
+static int ohci_hcd_at91_drv_remove(struct device *dev)
+{
+	usb_hcd_at91_remove(dev_get_drvdata(dev), to_platform_device(dev));
+	dev_set_drvdata(dev, NULL);
+	return 0;
+}
+
+#if defined(CONFIG_USB_SUSPEND) || defined(CONFIG_PM)
+
+static int ohci_hcd_at91_drv_suspend(struct device *dev, u32 state, u32 level)
+{
+  //	struct platform_device *pdev = to_platform_device(dev);
+  //	struct usb_hcd *hcd = dev_get_drvdata(dev);
+	printk("%s(%s:%d): not implemented yet\n",
+		__func__, __FILE__, __LINE__);
+
+	return 0;
+}
+
+static int ohci_hcd_at91_drv_resume(struct device *dev, u32 state)
+{
+//	struct platform_device *pdev = to_platform_device(dev);
+//	struct usb_hcd *hcd = dev_get_drvdata(dev);
+	printk("%s(%s:%d): not implemented yet\n",
+		__func__, __FILE__, __LINE__);
+
+	return 0;
+}
+
+#endif
+
+static struct device_driver ohci_hcd_at91_driver = {
+	.name		= "at91rm9200-ohci",
+	.bus		= &platform_bus_type,
+	.probe		= ohci_hcd_at91_drv_probe,
+	.remove		= ohci_hcd_at91_drv_remove,
+#if defined(CONFIG_USB_SUSPEND) || defined(CONFIG_PM)
+	.suspend	= ohci_hcd_at91_drv_suspend,
+	.resume		= ohci_hcd_at91_drv_resume,
+#endif
+};
+
+static int __init ohci_hcd_at91_init (void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+	
+	return driver_register(&ohci_hcd_at91_driver);
+}
+
+static void __exit ohci_hcd_at91_cleanup (void)
+{
+	driver_unregister(&ohci_hcd_at91_driver);
+}
+
+module_init (ohci_hcd_at91_init);
+module_exit (ohci_hcd_at91_cleanup);
diff -urN linux-2.6.11-rc5.orig/drivers/usb/host/ohci-hcd.c linux-2.6.11-rc5/drivers/usb/host/ohci-hcd.c
--- linux-2.6.11-rc5.orig/drivers/usb/host/ohci-hcd.c	Fri Feb 25 11:51:43 2005
+++ linux-2.6.11-rc5/drivers/usb/host/ohci-hcd.c	Fri Feb 25 11:55:46 2005
@@ -901,12 +901,17 @@
 #include "ohci-au1xxx.c"
 #endif
 
+#ifdef CONFIG_ARCH_AT91RM9200
+#include "ohci-at91.c"
+#endif
+
 #if !(defined(CONFIG_PCI) \
       || defined(CONFIG_SA1111) \
       || defined(CONFIG_ARCH_OMAP) \
       || defined (CONFIG_ARCH_LH7A404) \
       || defined (CONFIG_PXA27x) \
       || defined (CONFIG_SOC_AU1X00) \
+      || defined (CONFIG_ARCH_AT91RM9200) \
 	)
 #error "missing bus glue for ohci-hcd"
 #endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,434 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 definitions
+// Generated           : AT91 SW Application Group  04/16/2003 (12:30:06)
+//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_H
+#define AT91RM9200_H
+
+#ifndef __ASSEMBLY__
+
+ /* Hardware register definition */
+typedef volatile unsigned int AT91_REG;
+
+#endif	/* __ASSEMBLY__ */
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91RM9200
+// *****************************************************************************
+#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ( 1) // System Peripheral
+#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
+#define AT91C_ID_PIOC   ( 4) // Parallel IO Controller C
+#define AT91C_ID_PIOD   ( 5) // Parallel IO Controller D
+#define AT91C_ID_US0    ( 6) // USART 0
+#define AT91C_ID_US1    ( 7) // USART 1
+#define AT91C_ID_US2    ( 8) // USART 2
+#define AT91C_ID_US3    ( 9) // USART 3
+#define AT91C_ID_MCI    (10) // Multimedia Card Interface
+#define AT91C_ID_UDP    (11) // USB Device Port
+#define AT91C_ID_TWI    (12) // Two-Wire Interface
+#define AT91C_ID_SPI    (13) // Serial Peripheral Interface
+#define AT91C_ID_SSC0   (14) // Serial Synchronous Controller 0
+#define AT91C_ID_SSC1   (15) // Serial Synchronous Controller 1
+#define AT91C_ID_SSC2   (16) // Serial Synchronous Controller 2
+#define AT91C_ID_TC0    (17) // Timer Counter 0
+#define AT91C_ID_TC1    (18) // Timer Counter 1
+#define AT91C_ID_TC2    (19) // Timer Counter 2
+#define AT91C_ID_TC3    (20) // Timer Counter 3
+#define AT91C_ID_TC4    (21) // Timer Counter 4
+#define AT91C_ID_TC5    (22) // Timer Counter 5
+#define AT91C_ID_UHP    (23) // USB Host port
+#define AT91C_ID_EMAC   (24) // Ethernet MAC
+#define AT91C_ID_IRQ0   (25) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   (26) // Advanced Interrupt Controller (IRQ1)
+#define AT91C_ID_IRQ2   (27) // Advanced Interrupt Controller (IRQ2)
+#define AT91C_ID_IRQ3   (28) // Advanced Interrupt Controller (IRQ3)
+#define AT91C_ID_IRQ4   (29) // Advanced Interrupt Controller (IRQ4)
+#define AT91C_ID_IRQ5   (30) // Advanced Interrupt Controller (IRQ5)
+#define AT91C_ID_IRQ6   (31) // Advanced Interrupt Controller (IRQ6)
+
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91RM9200
+// *****************************************************************************
+#define AT91C_BASE_SYS		(0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_PDC_SPI	(0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI		(0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_SSC2	(0xFFFD8100) // (PDC_SSC2) Base Address
+#define AT91C_BASE_SSC2		(0xFFFD8000) // (SSC2) Base Address
+#define AT91C_BASE_PDC_SSC1	(0xFFFD4100) // (PDC_SSC1) Base Address
+#define AT91C_BASE_SSC1		(0xFFFD4000) // (SSC1) Base Address
+#define AT91C_BASE_PDC_SSC0	(0xFFFD0100) // (PDC_SSC0) Base Address
+#define AT91C_BASE_SSC0		(0xFFFD0000) // (SSC0) Base Address
+#define AT91C_BASE_PDC_US3	(0xFFFCC100) // (PDC_US3) Base Address
+#define AT91C_BASE_US3		(0xFFFCC000) // (US3) Base Address
+#define AT91C_BASE_PDC_US2	(0xFFFC8100) // (PDC_US2) Base Address
+#define AT91C_BASE_US2		(0xFFFC8000) // (US2) Base Address
+#define AT91C_BASE_PDC_US1	(0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1		(0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0	(0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0		(0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_EMAC		(0xFFFBC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_MCI	(0xFFFB4100) // (PDC_MCI) Base Address
+#define AT91C_BASE_TWI		(0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_MCI		(0xFFFB4000) // (MCI) Base Address
+#define AT91C_BASE_UDP		(0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC5		(0xFFFA4080) // (TC5) Base Address
+#define AT91C_BASE_TC4		(0xFFFA4040) // (TC4) Base Address
+#define AT91C_BASE_TC3		(0xFFFA4000) // (TC3) Base Address
+#define AT91C_BASE_TCB1		(0xFFFA4000) // (TCB1) Base Address
+#define AT91C_BASE_TC2		(0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC1		(0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC0		(0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TCB0		(0xFFFA0000) // (TCB0) Base Address
+
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91RM9200
+// *****************************************************************************
+#define AT91C_PIO_PA0		(1 <<  0)
+#define AT91C_PA0_MISO		(AT91C_PIO_PA0) //  SPI Master In Slave
+#define AT91C_PA0_PCK3		(AT91C_PIO_PA0) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA1		(1 <<  1)
+#define AT91C_PA1_MOSI		(AT91C_PIO_PA1) //  SPI Master Out Slave
+#define AT91C_PA1_PCK0		(AT91C_PIO_PA1) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PA2		(1 <<  2)
+#define AT91C_PA2_SPCK		(AT91C_PIO_PA2) //  SPI Serial Clock
+#define AT91C_PA2_IRQ4		(AT91C_PIO_PA2) //  AIC Interrupt Input 4
+#define AT91C_PIO_PA3		(1 <<  3)
+#define AT91C_PA3_NPCS0		(AT91C_PIO_PA3) //  SPI Peripheral Chip Select 0
+#define AT91C_PA3_IRQ5		(AT91C_PIO_PA3) //  AIC Interrupt Input 5
+#define AT91C_PIO_PA4		(1 <<  4)
+#define AT91C_PA4_NPCS1		(AT91C_PIO_PA4) //  SPI Peripheral Chip Select 1
+#define AT91C_PA4_PCK1		(AT91C_PIO_PA4) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA5		(1 <<  5)
+#define AT91C_PA5_NPCS2		(AT91C_PIO_PA5) //  SPI Peripheral Chip Select 2
+#define AT91C_PA5_TXD3		(AT91C_PIO_PA5) //  USART 3 Transmit Data
+#define AT91C_PIO_PA6		(1 <<  6)
+#define AT91C_PA6_NPCS3		(AT91C_PIO_PA6) //  SPI Peripheral Chip Select 3
+#define AT91C_PA6_RXD3		(AT91C_PIO_PA6) //  USART 3 Receive Data
+#define AT91C_PIO_PA7		(1 <<  7)
+#define AT91C_PA7_ETXCK_EREFCK	(AT91C_PIO_PA7) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PA7_PCK2		(AT91C_PIO_PA7) //  PMC Programmable Clock 2
+#define AT91C_PIO_PA8		(1 <<  8)
+#define AT91C_PA8_ETXEN		(AT91C_PIO_PA8) //  Ethernet MAC Transmit Enable
+#define AT91C_PA8_MCCDB		(AT91C_PIO_PA8) //  Multimedia Card B Command
+#define AT91C_PIO_PA9		(1 <<  9)
+#define AT91C_PA9_ETX0		(AT91C_PIO_PA9) //  Ethernet MAC Transmit Data 0
+#define AT91C_PA9_MCDB0		(AT91C_PIO_PA9) //  Multimedia Card B Data 0
+#define AT91C_PIO_PA10		(1 << 10)
+#define AT91C_PA10_ETX1		(AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 1
+#define AT91C_PA10_MCDB1	(AT91C_PIO_PA10) //  Multimedia Card B Data 1
+#define AT91C_PIO_PA11		(1 << 11)
+#define AT91C_PA11_ECRS_ECRSDV	(AT91C_PIO_PA11) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PA11_MCDB2	(AT91C_PIO_PA11) //  Multimedia Card B Data 2
+#define AT91C_PIO_PA12		(1 << 12)
+#define AT91C_PA12_ERX0		(AT91C_PIO_PA12) //  Ethernet MAC Receive Data 0
+#define AT91C_PA12_MCDB3	(AT91C_PIO_PA12) //  Multimedia Card B Data 3
+#define AT91C_PIO_PA13 		(1 << 13)
+#define AT91C_PA13_ERX1		(AT91C_PIO_PA13) //  Ethernet MAC Receive Data 1
+#define AT91C_PA13_TCLK0	(AT91C_PIO_PA13) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PA14		(1 << 14)
+#define AT91C_PA14_ERXER	(AT91C_PIO_PA14) //  Ethernet MAC Receive Error
+#define AT91C_PA14_TCLK1	(AT91C_PIO_PA14) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PA15		(1 << 15)
+#define AT91C_PA15_EMDC		(AT91C_PIO_PA15) //  Ethernet MAC Management Data Clock
+#define AT91C_PA15_TCLK2	(AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16		(1 << 16)
+#define AT91C_PA16_EMDIO	(AT91C_PIO_PA16) //  Ethernet MAC Management Data Input/Output
+#define AT91C_PA16_IRQ6		(AT91C_PIO_PA16) //  AIC Interrupt input 6
+#define AT91C_PIO_PA17		(1 << 17)
+#define AT91C_PA17_TXD0		(AT91C_PIO_PA17) //  USART 0 Transmit Data
+#define AT91C_PA17_TIOA0	(AT91C_PIO_PA17) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA18		(1 << 18)
+#define AT91C_PA18_RXD0		(AT91C_PIO_PA18) //  USART 0 Receive Data
+#define AT91C_PA18_TIOB0	(AT91C_PIO_PA18) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA19		(1 << 19)
+#define AT91C_PA19_SCK0		(AT91C_PIO_PA19) //  USART 0 Serial Clock
+#define AT91C_PA19_TIOA1	(AT91C_PIO_PA19) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA20		(1 << 20)
+#define AT91C_PA20_CTS0		(AT91C_PIO_PA20) //  USART 0 Clear To Send
+#define AT91C_PA20_TIOB1	(AT91C_PIO_PA20) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA21		(1 << 21)
+#define AT91C_PA21_RTS0		(AT91C_PIO_PA21) //  USART 0 Ready To Send
+#define AT91C_PA21_TIOA2	(AT91C_PIO_PA21) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA22		(1 << 22)
+#define AT91C_PA22_RXD2		(AT91C_PIO_PA22) //  USART 2 Receive Data
+#define AT91C_PA22_TIOB2	(AT91C_PIO_PA22) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA23		(1 << 23)
+#define AT91C_PA23_TXD2		(AT91C_PIO_PA23) //  USART 2 Transmit Data
+#define AT91C_PA23_IRQ3		(AT91C_PIO_PA23) //  Interrupt input 3
+#define AT91C_PIO_PA24		(1 << 24)
+#define AT91C_PA24_SCK2		(AT91C_PIO_PA24) //  USART 2 Serial Clock
+#define AT91C_PA24_PCK1		(AT91C_PIO_PA24) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA25		(1 << 25)
+#define AT91C_PA25_TWD		(AT91C_PIO_PA25) //  TWI Two-wire Serial Data
+#define AT91C_PA25_IRQ2		(AT91C_PIO_PA25) //  Interrupt input 2
+#define AT91C_PIO_PA26		(1 << 26)
+#define AT91C_PA26_TWCK		(AT91C_PIO_PA26) //  TWI Two-wire Serial Clock
+#define AT91C_PA26_IRQ1		(AT91C_PIO_PA26) //  Interrupt input 1
+#define AT91C_PIO_PA27		(1 << 27)
+#define AT91C_PA27_MCCK		(AT91C_PIO_PA27) //  Multimedia Card Clock
+#define AT91C_PA27_TCLK3	(AT91C_PIO_PA27) //  Timer Counter 3 External Clock Input
+#define AT91C_PIO_PA28		(1 << 28)
+#define AT91C_PA28_MCCDA	(AT91C_PIO_PA28) //  Multimedia Card A Command
+#define AT91C_PA28_TCLK4	(AT91C_PIO_PA28) //  Timer Counter 4 external Clock Input
+#define AT91C_PIO_PA29		(1 << 29)
+#define AT91C_PA29_MCDA0	(AT91C_PIO_PA29) //  Multimedia Card A Data 0
+#define AT91C_PA29_TCLK5	(AT91C_PIO_PA29) //  Timer Counter 5 external clock input
+#define AT91C_PIO_PA30		(1 << 30)
+#define AT91C_PA30_DRXD		(AT91C_PIO_PA30) //  DBGU Debug Receive Data
+#define AT91C_PA30_CTS2		(AT91C_PIO_PA30) //  USART 2 Clear To Send
+#define AT91C_PIO_PA31		(1 << 31)
+#define AT91C_PA31_DTXD		(AT91C_PIO_PA31) //  DBGU Debug Transmit Data
+#define AT91C_PA31_RTS2		(AT91C_PIO_PA31) //  USART 2 Ready To Send
+
+#define AT91C_PIO_PB0		(1 <<  0)
+#define AT91C_PB0_TF0		(AT91C_PIO_PB0) //  SSC Transmit Frame Sync 0
+#define AT91C_PB0_RTS3		(AT91C_PIO_PB0) //  USART 3 Ready To Send
+#define AT91C_PIO_PB1		(1 <<  1)
+#define AT91C_PB1_TK0		(AT91C_PIO_PB1) //  SSC Transmit Clock 0
+#define AT91C_PB1_CTS3		(AT91C_PIO_PB1) //  USART 3 Clear To Send
+#define AT91C_PIO_PB2		(1 <<  2)
+#define AT91C_PB2_TD0		(AT91C_PIO_PB2) //  SSC Transmit data
+#define AT91C_PB2_SCK3		(AT91C_PIO_PB2) //  USART 3 Serial Clock
+#define AT91C_PIO_PB3		(1 <<  3)
+#define AT91C_PB3_RD0		(AT91C_PIO_PB3) //  SSC Receive Data
+#define AT91C_PB3_MCDA1		(AT91C_PIO_PB3) //  Multimedia Card A Data 1
+#define AT91C_PIO_PB4		(1 <<  4)
+#define AT91C_PB4_RK0		(AT91C_PIO_PB4) //  SSC Receive Clock
+#define AT91C_PB4_MCDA2		(AT91C_PIO_PB4) //  Multimedia Card A Data 2
+#define AT91C_PIO_PB5		(1 <<  5)
+#define AT91C_PB5_RF0		(AT91C_PIO_PB5) //  SSC Receive Frame Sync 0
+#define AT91C_PB5_MCDA3		(AT91C_PIO_PB5) //  Multimedia Card A Data 3
+#define AT91C_PIO_PB6		(1 <<  6)
+#define AT91C_PB6_TF1		(AT91C_PIO_PB6) //  SSC Transmit Frame Sync 1
+#define AT91C_PB6_TIOA3		(AT91C_PIO_PB6) //  Timer Counter 4 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB7		(1 <<  7)
+#define AT91C_PB7_TK1		(AT91C_PIO_PB7) //  SSC Transmit Clock 1
+#define AT91C_PB7_TIOB3		(AT91C_PIO_PB7) //  Timer Counter 3 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB8		(1 <<  8)
+#define AT91C_PB8_TD1		(AT91C_PIO_PB8) //  SSC Transmit Data 1
+#define AT91C_PB8_TIOA4		(AT91C_PIO_PB8) //  Timer Counter 4 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB9		(1 <<  9)
+#define AT91C_PB9_RD1		(AT91C_PIO_PB9) //  SSC Receive Data 1
+#define AT91C_PB9_TIOB4		(AT91C_PIO_PB9) //  Timer Counter 4 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB10		(1 << 10)
+#define AT91C_PB10_RK1		(AT91C_PIO_PB10) //  SSC Receive Clock 1
+#define AT91C_PB10_TIOA5	(AT91C_PIO_PB10) //  Timer Counter 5 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB11		(1 << 11)
+#define AT91C_PB11_RF1		(AT91C_PIO_PB11) //  SSC Receive Frame Sync 1
+#define AT91C_PB11_TIOB5	(AT91C_PIO_PB11) //  Timer Counter 5 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB12		(1 << 12)
+#define AT91C_PB12_TF2		(AT91C_PIO_PB12) //  SSC Transmit Frame Sync 2
+#define AT91C_PB12_ETX2		(AT91C_PIO_PB12) //  Ethernet MAC Transmit Data 2
+#define AT91C_PIO_PB13		(1 << 13)
+#define AT91C_PB13_TK2		(AT91C_PIO_PB13) //  SSC Transmit Clock 2
+#define AT91C_PB13_ETX3		(AT91C_PIO_PB13) //  Ethernet MAC Transmit Data 3
+#define AT91C_PIO_PB14		(1 << 14)
+#define AT91C_PB14_TD2		(AT91C_PIO_PB14) //  SSC Transmit Data 2
+#define AT91C_PB14_ETXER	(AT91C_PIO_PB14) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PIO_PB15		(1 << 15)
+#define AT91C_PB15_RD2		(AT91C_PIO_PB15) //  SSC Receive Data 2
+#define AT91C_PB15_ERX2		(AT91C_PIO_PB15) //  Ethernet MAC Receive Data 2
+#define AT91C_PIO_PB16		(1 << 16)
+#define AT91C_PB16_RK2		(AT91C_PIO_PB16) //  SSC Receive Clock 2
+#define AT91C_PB16_ERX3		(AT91C_PIO_PB16) //  Ethernet MAC Receive Data 3
+#define AT91C_PIO_PB17		(1 << 17)
+#define AT91C_PB17_RF2		(AT91C_PIO_PB17) //  SSC Receive Frame Sync 2
+#define AT91C_PB17_ERXDV	(AT91C_PIO_PB17) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB18		(1 << 18)
+#define AT91C_PB18_RI1		(AT91C_PIO_PB18) //  USART 1 Ring Indicator
+#define AT91C_PB18_ECOL		(AT91C_PIO_PB18) //  Ethernet MAC Collision Detected
+#define AT91C_PIO_PB19		(1 << 19)
+#define AT91C_PB19_DTR1		(AT91C_PIO_PB19) //  USART 1 Data Terminal ready
+#define AT91C_PB19_ERXCK	(AT91C_PIO_PB19) //  Ethernet MAC Receive Clock
+#define AT91C_PIO_PB20		(1 << 20)
+#define AT91C_PB20_TXD1		(AT91C_PIO_PB20) //  USART 1 Transmit Data
+#define AT91C_PIO_PB21		(1 << 21)
+#define AT91C_PB21_RXD1		(AT91C_PIO_PB21) //  USART 1 Receive Data
+#define AT91C_PIO_PB22		(1 << 22)
+#define AT91C_PB22_SCK1		(AT91C_PIO_PB22) //  USART 1 Serial Clock
+#define AT91C_PIO_PB23		(1 << 23)
+#define AT91C_PB23_DCD1		(AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24		(1 << 24)
+#define AT91C_PB24_CTS1		(AT91C_PIO_PB24) //  USART 1 Clear To Send
+#define AT91C_PIO_PB25		(1 << 25)
+#define AT91C_PB25_DSR1		(AT91C_PIO_PB25) //  USART 1 Data Set ready
+#define AT91C_PB25_EF100	(AT91C_PIO_PB25) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PIO_PB26		(1 << 26)
+#define AT91C_PB26_RTS1		(AT91C_PIO_PB26) //  USART 1 Ready To Send
+#define AT91C_PIO_PB27		(1 << 27)
+#define AT91C_PB27_PCK0		(AT91C_PIO_PB27) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB28		(1 << 28)
+#define AT91C_PB28_FIQ		(AT91C_PIO_PB28) //  AIC Fast Interrupt Input
+#define AT91C_PIO_PB29		(1 << 29)
+#define AT91C_PB29_IRQ0		(AT91C_PIO_PB29) //  Interrupt input 0
+
+#define AT91C_PIO_PC0		(1 <<  0)
+#define AT91C_PC0_BFCK		(AT91C_PIO_PC0) //  Burst Flash Clock
+#define AT91C_PIO_PC1		(1 <<  1)
+#define AT91C_PC1_BFRDY_SMOE	(AT91C_PIO_PC1) //  Burst Flash Ready
+#define AT91C_PIO_PC2		(1 <<  2)
+#define AT91C_PC2_BFAVD		(AT91C_PIO_PC2) //  Burst Flash Address Valid
+#define AT91C_PIO_PC3		(1 <<  3)
+#define AT91C_PC3_BFBAA_SMWE	(AT91C_PIO_PC3) //  Burst Flash Address Advance / SmartMedia Write Enable
+#define AT91C_PIO_PC4		(1 <<  4)
+#define AT91C_PC4_BFOE		(AT91C_PIO_PC4) //  Burst Flash Output Enable
+#define AT91C_PIO_PC5		(1 <<  5)
+#define AT91C_PC5_BFWE		(AT91C_PIO_PC5) //  Burst Flash Write Enable
+#define AT91C_PIO_PC6		(1 <<  6)
+#define AT91C_PC6_NWAIT		(AT91C_PIO_PC6) //  NWAIT
+#define AT91C_PIO_PC7		(1 <<  7)
+#define AT91C_PC7_A23		(AT91C_PIO_PC7) //  Address Bus[23]
+#define AT91C_PIO_PC8		(1 <<  8)
+#define AT91C_PC8_A24		(AT91C_PIO_PC8) //  Address Bus[24]
+#define AT91C_PIO_PC9		(1 <<  9)
+#define AT91C_PC9_A25_CFRNW	(AT91C_PIO_PC9) //  Address Bus[25] /  Compact Flash Read Not Write
+#define AT91C_PIO_PC10		(1 << 10)
+#define AT91C_PC10_NCS4_CFCS	(AT91C_PIO_PC10) //  Compact Flash Chip Select
+#define AT91C_PIO_PC11		(1 << 11)
+#define AT91C_PC11_NCS5_CFCE1	(AT91C_PIO_PC11) //  Chip Select 5 / Compact Flash Chip Enable 1
+#define AT91C_PIO_PC12		(1 << 12)
+#define AT91C_PC12_NCS6_CFCE2	(AT91C_PIO_PC12) //  Chip Select 6 / Compact Flash Chip Enable 2
+#define AT91C_PIO_PC13		(1 << 13)
+#define AT91C_PC13_NCS7		(AT91C_PIO_PC13) //  Chip Select 7
+#define AT91C_PIO_PC14		(1 << 14)
+#define AT91C_PIO_PC15		(1 << 15)
+#define AT91C_PIO_PC16		(1 << 16)
+#define AT91C_PC16_D16		(AT91C_PIO_PC16) //  Data Bus [16]
+#define AT91C_PIO_PC17		(1 << 17)
+#define AT91C_PC17_D17		(AT91C_PIO_PC17) //  Data Bus [17]
+#define AT91C_PIO_PC18		(1 << 18)
+#define AT91C_PC18_D18		(AT91C_PIO_PC18) //  Data Bus [18]
+#define AT91C_PIO_PC19		(1 << 19)
+#define AT91C_PC19_D19		(AT91C_PIO_PC19) //  Data Bus [19]
+#define AT91C_PIO_PC20		(1 << 20)
+#define AT91C_PC20_D20		(AT91C_PIO_PC20) //  Data Bus [20]
+#define AT91C_PIO_PC21		(1 << 21)
+#define AT91C_PC21_D21		(AT91C_PIO_PC21) //  Data Bus [21]
+#define AT91C_PIO_PC22		(1 << 22)
+#define AT91C_PC22_D22		(AT91C_PIO_PC22) //  Data Bus [22]
+#define AT91C_PIO_PC23		(1 << 23)
+#define AT91C_PC23_D23		(AT91C_PIO_PC23) //  Data Bus [23]
+#define AT91C_PIO_PC24		(1 << 24)
+#define AT91C_PC24_D24		(AT91C_PIO_PC24) //  Data Bus [24]
+#define AT91C_PIO_PC25		(1 << 25)
+#define AT91C_PC25_D25		(AT91C_PIO_PC25) //  Data Bus [25]
+#define AT91C_PIO_PC26		(1 << 26)
+#define AT91C_PC26_D26		(AT91C_PIO_PC26) //  Data Bus [26]
+#define AT91C_PIO_PC27		(1 << 27)
+#define AT91C_PC27_D27		(AT91C_PIO_PC27) //  Data Bus [27]
+#define AT91C_PIO_PC28		(1 << 28)
+#define AT91C_PC28_D28		(AT91C_PIO_PC28) //  Data Bus [28]
+#define AT91C_PIO_PC29		(1 << 29)
+#define AT91C_PC29_D29		(AT91C_PIO_PC29) //  Data Bus [29]
+#define AT91C_PIO_PC30		(1 << 30)
+#define AT91C_PC30_D30		(AT91C_PIO_PC30) //  Data Bus [30]
+#define AT91C_PIO_PC31		(1 << 31)
+#define AT91C_PC31_D31		(AT91C_PIO_PC31) //  Data Bus [31]
+
+#define AT91C_PIO_PD0		(1 <<  0)
+#define AT91C_PD0_ETX0		(AT91C_PIO_PD0) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PD1		(1 <<  1)
+#define AT91C_PD1_ETX1		(AT91C_PIO_PD1) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PD2		(1 <<  2)
+#define AT91C_PD2_ETX2		(AT91C_PIO_PD2) //  Ethernet MAC Transmit Data 2
+#define AT91C_PIO_PD3		(1 <<  3)
+#define AT91C_PD3_ETX3		(AT91C_PIO_PD3) //  Ethernet MAC Transmit Data 3
+#define AT91C_PIO_PD4		(1 <<  4)
+#define AT91C_PD4_ETXEN		(AT91C_PIO_PD4) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PD5		(1 <<  5)
+#define AT91C_PD5_ETXER		(AT91C_PIO_PD5) //  Ethernet MAC Transmit Coding Error
+#define AT91C_PIO_PD6		(1 <<  6)
+#define AT91C_PD6_DTXD		(AT91C_PIO_PD6) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PD7		(1 <<  7)
+#define AT91C_PD7_PCK0		(AT91C_PIO_PD7) //  PMC Programmable Clock Output 0
+#define AT91C_PD7_TSYNC		(AT91C_PIO_PD7) //  ETM Synchronization signal
+#define AT91C_PIO_PD8		(1 <<  8)
+#define AT91C_PD8_PCK1		(AT91C_PIO_PD8) //  PMC Programmable Clock Output 1
+#define AT91C_PD8_TCLK		(AT91C_PIO_PD8) //  ETM Trace Clock signal
+#define AT91C_PIO_PD9		(1 <<  9)
+#define AT91C_PD9_PCK2		(AT91C_PIO_PD9) //  PMC Programmable Clock 2
+#define AT91C_PD9_TPS0		(AT91C_PIO_PD9) //  ETM ARM9 pipeline status 0
+#define AT91C_PIO_PD10		(1 << 10)
+#define AT91C_PD10_PCK3		(AT91C_PIO_PD10) //  PMC Programmable Clock Output 3
+#define AT91C_PD10_TPS1		(AT91C_PIO_PD10) //  ETM ARM9 pipeline status 1
+#define AT91C_PIO_PD11		(1 << 11)
+#define AT91C_PD11_TPS2		(AT91C_PIO_PD11) //  ETM ARM9 pipeline status 2
+#define AT91C_PIO_PD12		(1 << 12)
+#define AT91C_PD12_TPK0		(AT91C_PIO_PD12) //  ETM Trace Packet 0
+#define AT91C_PIO_PD13		(1 << 13)
+#define AT91C_PD13_TPK1		(AT91C_PIO_PD13) //  ETM Trace Packet 1
+#define AT91C_PIO_PD14		(1 << 14)
+#define AT91C_PD14_TPK2		(AT91C_PIO_PD14) //  ETM Trace Packet 2
+#define AT91C_PIO_PD15		(1 << 15)
+#define AT91C_PD15_TD0		(AT91C_PIO_PD15) //  SSC Transmit data
+#define AT91C_PD15_TPK3		(AT91C_PIO_PD15) //  ETM Trace Packet 3
+#define AT91C_PIO_PD16		(1 << 16)
+#define AT91C_PD16_TD1		(AT91C_PIO_PD16) //  SSC Transmit Data 1
+#define AT91C_PD16_TPK4		(AT91C_PIO_PD16) //  ETM Trace Packet 4
+#define AT91C_PIO_PD17		(1 << 17)
+#define AT91C_PD17_TD2		(AT91C_PIO_PD17) //  SSC Transmit Data 2
+#define AT91C_PD17_TPK5		(AT91C_PIO_PD17) //  ETM Trace Packet 5
+#define AT91C_PIO_PD18		(1 << 18)
+#define AT91C_PD18_NPCS1	(AT91C_PIO_PD18) //  SPI Peripheral Chip Select 1
+#define AT91C_PD18_TPK6		(AT91C_PIO_PD18) //  ETM Trace Packet 6
+#define AT91C_PIO_PD19		(1 << 19)
+#define AT91C_PD19_NPCS2	(AT91C_PIO_PD19) //  SPI Peripheral Chip Select 2
+#define AT91C_PD19_TPK7		(AT91C_PIO_PD19) //  ETM Trace Packet 7
+#define AT91C_PIO_PD20		(1 << 20)
+#define AT91C_PD20_NPCS3	(AT91C_PIO_PD20) //  SPI Peripheral Chip Select 3
+#define AT91C_PD20_TPK8		(AT91C_PIO_PD20) //  ETM Trace Packet 8
+#define AT91C_PIO_PD21		(1 << 21)
+#define AT91C_PD21_RTS0		(AT91C_PIO_PD21) //  Usart 0 Ready To Send
+#define AT91C_PD21_TPK9		(AT91C_PIO_PD21) //  ETM Trace Packet 9
+#define AT91C_PIO_PD22		(1 << 22)
+#define AT91C_PD22_RTS1		(AT91C_PIO_PD22) //  Usart 0 Ready To Send
+#define AT91C_PD22_TPK10	(AT91C_PIO_PD22) //  ETM Trace Packet 10
+#define AT91C_PIO_PD23		(1 << 23)
+#define AT91C_PD23_RTS2		(AT91C_PIO_PD23) //  USART 2 Ready To Send
+#define AT91C_PD23_TPK11	(AT91C_PIO_PD23) //  ETM Trace Packet 11
+#define AT91C_PIO_PD24		(1 << 24)
+#define AT91C_PD24_RTS3		(AT91C_PIO_PD24) //  USART 3 Ready To Send
+#define AT91C_PD24_TPK12	(AT91C_PIO_PD24) //  ETM Trace Packet 12
+#define AT91C_PIO_PD25		(1 << 25)
+#define AT91C_PD25_DTR1		(AT91C_PIO_PD25) //  USART 1 Data Terminal ready
+#define AT91C_PD25_TPK13	(AT91C_PIO_PD25) //  ETM Trace Packet 13
+#define AT91C_PIO_PD26		(1 << 26)
+#define AT91C_PD26_TPK14	(AT91C_PIO_PD26) //  ETM Trace Packet 14
+#define AT91C_PIO_PD27		(1 << 27)
+#define AT91C_PD27_TPK15	(AT91C_PIO_PD27) //  ETM Trace Packet 15
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_EMAC.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_EMAC.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_EMAC.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_EMAC.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,163 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 / EMAC definitions
+// Generated           : AT91 SW Application Group  01/17/2003 (13:41:21)
+//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_EMAC_H
+#define AT91RM9200_EMAC_H
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_CTL; 	// Network Control Register
+	AT91_REG	 EMAC_CFG; 	// Network Configuration Register
+	AT91_REG	 EMAC_SR; 	// Network Status Register
+	AT91_REG	 EMAC_TAR; 	// Transmit Address Register
+	AT91_REG	 EMAC_TCR; 	// Transmit Control Register
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 Reserved0[1]; 	//
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 Reserved1[2]; 	//
+	AT91_REG	 EMAC_FRA; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCOL; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCOL; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_OK; 	// Frames Received OK Register
+	AT91_REG	 EMAC_SEQE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTE; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_TUE; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CDE; 	// Code Error Register
+	AT91_REG	 EMAC_ELR; 	// Excessive Length Error Register
+	AT91_REG	 EMAC_RJB; 	// Receive Jabber Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frame Register
+	AT91_REG	 EMAC_SQEE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_DRFC; 	// Discarded RX Frame Register
+	AT91_REG	 Reserved2[3]; 	//
+	AT91_REG	 EMAC_HSH; 	// Hash Address High[63:32]
+	AT91_REG	 EMAC_HSL; 	// Hash Address Low[31:0]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Low, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 High, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Low, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 High, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Low, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 High, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Low, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 High, Last 2 bytesr
+} AT91S_EMAC, *AT91PS_EMAC;
+
+#endif
+
+// -------- EMAC_CTL : (EMAC Offset: 0x0)  --------
+#define AT91C_EMAC_LB         ( 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LBL        ( 0x1 <<  1) // (EMAC) Loopback local.
+#define AT91C_EMAC_RE         ( 0x1 <<  2) // (EMAC) Receive enable.
+#define AT91C_EMAC_TE         ( 0x1 <<  3) // (EMAC) Transmit enable.
+#define AT91C_EMAC_MPE        ( 0x1 <<  4) // (EMAC) Management port enable.
+#define AT91C_EMAC_CSR        ( 0x1 <<  5) // (EMAC) Clear statistics registers.
+#define AT91C_EMAC_ISR        ( 0x1 <<  6) // (EMAC) Increment statistics registers.
+#define AT91C_EMAC_WES        ( 0x1 <<  7) // (EMAC) Write enable for statistics registers.
+#define AT91C_EMAC_BP         ( 0x1 <<  8) // (EMAC) Back pressure.
+// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------
+#define AT91C_EMAC_SPD        ( 0x1 <<  0) // (EMAC) Speed.
+#define AT91C_EMAC_FD         ( 0x1 <<  1) // (EMAC) Full duplex.
+#define AT91C_EMAC_BR         ( 0x1 <<  2) // (EMAC) Bit rate.
+#define AT91C_EMAC_CAF        ( 0x1 <<  4) // (EMAC) Copy all frames.
+#define AT91C_EMAC_NBC        ( 0x1 <<  5) // (EMAC) No broadcast.
+#define AT91C_EMAC_MTI        ( 0x1 <<  6) // (EMAC) Multicast hash enable
+#define AT91C_EMAC_UNI        ( 0x1 <<  7) // (EMAC) Unicast hash enable.
+#define AT91C_EMAC_BIG        ( 0x1 <<  8) // (EMAC) Receive 1522 bytes.
+#define AT91C_EMAC_EAE        ( 0x1 <<  9) // (EMAC) External address match enable.
+#define AT91C_EMAC_CLK        ( 0x3 << 10) // (EMAC)
+#define 	AT91C_EMAC_CLK_HCLK_8               ( 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ( 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ( 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ( 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ( 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_RMII       ( 0x1 << 13) // (EMAC)
+// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------
+#define AT91C_EMAC_MDIO       ( 0x1 <<  1) // (EMAC)
+#define AT91C_EMAC_IDLE       ( 0x1 <<  2) // (EMAC)
+// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register --------
+#define AT91C_EMAC_LEN        ( 0x7FF <<  0) // (EMAC)
+#define AT91C_EMAC_NCRC       ( 0x1 << 15) // (EMAC)
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register --------
+#define AT91C_EMAC_OVR        ( 0x1 <<  0) // (EMAC)
+#define AT91C_EMAC_COL        ( 0x1 <<  1) // (EMAC)
+#define AT91C_EMAC_RLE        ( 0x1 <<  2) // (EMAC)
+#define AT91C_EMAC_TXIDLE     ( 0x1 <<  3) // (EMAC)
+#define AT91C_EMAC_BNQ        ( 0x1 <<  4) // (EMAC)
+#define AT91C_EMAC_COMP       ( 0x1 <<  5) // (EMAC)
+#define AT91C_EMAC_UND        ( 0x1 <<  6) // (EMAC)
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+#define AT91C_EMAC_BNA        ( 0x1 <<  0) // (EMAC)
+#define AT91C_EMAC_REC        ( 0x1 <<  1) // (EMAC)
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+#define AT91C_EMAC_DONE       ( 0x1 <<  0) // (EMAC)
+#define AT91C_EMAC_RCOM       ( 0x1 <<  1) // (EMAC)
+#define AT91C_EMAC_RBNA       ( 0x1 <<  2) // (EMAC)
+#define AT91C_EMAC_TOVR       ( 0x1 <<  3) // (EMAC)
+#define AT91C_EMAC_TUND       ( 0x1 <<  4) // (EMAC)
+#define AT91C_EMAC_RTRY       ( 0x1 <<  5) // (EMAC)
+#define AT91C_EMAC_TBRE       ( 0x1 <<  6) // (EMAC)
+#define AT91C_EMAC_TCOM       ( 0x1 <<  7) // (EMAC)
+#define AT91C_EMAC_TIDLE      ( 0x1 <<  8) // (EMAC)
+#define AT91C_EMAC_LINK       ( 0x1 <<  9) // (EMAC)
+#define AT91C_EMAC_ROVR       ( 0x1 << 10) // (EMAC)
+#define AT91C_EMAC_HRESP      ( 0x1 << 11) // (EMAC)
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+#define AT91C_EMAC_DATA       ( 0xFFFF <<  0) // (EMAC)
+#define AT91C_EMAC_CODE       ( 0x3 << 16) // (EMAC)
+#define         AT91C_EMAC_CODE_802_3 ( 0x2 << 16) // (EMAC) Write Operation
+#define AT91C_EMAC_REGA       ( 0x1F << 18) // (EMAC)
+#define AT91C_EMAC_PHYA       ( 0x1F << 23) // (EMAC)
+#define AT91C_EMAC_RW         ( 0x3 << 28) // (EMAC)
+#define         AT91C_EMAC_RW_R       ( 0x2 << 28) // (EMAC) Read Operation
+#define         AT91C_EMAC_RW_W       ( 0x1 << 28) // (EMAC) Write Operation
+#define AT91C_EMAC_HIGH       ( 0x1 << 30) // (EMAC)
+#define AT91C_EMAC_LOW        ( 0x1 << 31) // (EMAC)
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_MCI.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_MCI.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_MCI.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_MCI.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,146 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 / MCI definitions
+// Generated           : AT91 SW Application Group  12/03/2002 (10:48:02)
+// 
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_MCI_H
+#define AT91RM9200_MCI_H
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+
+typedef struct _AT91S_MCI {
+	AT91_REG	 MCI_CR; 	// MCI Control Register
+	AT91_REG	 MCI_MR; 	// MCI Mode Register
+	AT91_REG	 MCI_DTOR; 	// MCI Data Timeout Register
+	AT91_REG	 MCI_SDCR; 	// MCI SD Card Register
+	AT91_REG	 MCI_ARGR; 	// MCI Argument Register
+	AT91_REG	 MCI_CMDR; 	// MCI Command Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 MCI_RSPR[4]; 	// MCI Response Register
+	AT91_REG	 MCI_RDR; 	// MCI Receive Data Register
+	AT91_REG	 MCI_TDR; 	// MCI Transmit Data Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 MCI_SR; 	// MCI Status Register
+	AT91_REG	 MCI_IER; 	// MCI Interrupt Enable Register
+	AT91_REG	 MCI_IDR; 	// MCI Interrupt Disable Register
+	AT91_REG	 MCI_IMR; 	// MCI Interrupt Mask Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 MCI_RPR; 	// Receive Pointer Register
+	AT91_REG	 MCI_RCR; 	// Receive Counter Register
+	AT91_REG	 MCI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 MCI_TCR; 	// Transmit Counter Register
+	AT91_REG	 MCI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 MCI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 MCI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 MCI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 MCI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 MCI_PTSR; 	// PDC Transfer Status Register
+} AT91S_MCI, *AT91PS_MCI;
+
+#endif
+
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 
+#define AT91C_MCI_MCIEN       ((unsigned int) 0x1 <<  0) // (MCI) Multimedia Interface Enable
+#define AT91C_MCI_MCIDIS      ((unsigned int) 0x1 <<  1) // (MCI) Multimedia Interface Disable
+#define AT91C_MCI_PWSEN       ((unsigned int) 0x1 <<  2) // (MCI) Power Save Mode Enable
+#define AT91C_MCI_PWSDIS      ((unsigned int) 0x1 <<  3) // (MCI) Power Save Mode Disable
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 
+#define AT91C_MCI_CLKDIV      ((unsigned int) 0x1 <<  0) // (MCI) Clock Divider
+#define AT91C_MCI_PWSDIV      ((unsigned int) 0x1 <<  8) // (MCI) Power Saving Divider
+#define AT91C_MCI_PDCPADV     ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value
+#define AT91C_MCI_PDCMODE     ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode
+#define AT91C_MCI_BLKLEN      ((unsigned int) 0x1 << 18) // (MCI) Data Block Length
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 
+#define AT91C_MCI_DTOCYC      ((unsigned int) 0x1 <<  0) // (MCI) Data Timeout Cycle Number
+#define AT91C_MCI_DTOMUL      ((unsigned int) 0x7 <<  4) // (MCI) Data Timeout Multiplier
+#define 	AT91C_MCI_DTOMUL_1                    ((unsigned int) 0x0 <<  4) // (MCI) DTOCYC x 1
+#define 	AT91C_MCI_DTOMUL_16                   ((unsigned int) 0x1 <<  4) // (MCI) DTOCYC x 16
+#define 	AT91C_MCI_DTOMUL_128                  ((unsigned int) 0x2 <<  4) // (MCI) DTOCYC x 128
+#define 	AT91C_MCI_DTOMUL_256                  ((unsigned int) 0x3 <<  4) // (MCI) DTOCYC x 256
+#define 	AT91C_MCI_DTOMUL_1024                 ((unsigned int) 0x4 <<  4) // (MCI) DTOCYC x 1024
+#define 	AT91C_MCI_DTOMUL_4096                 ((unsigned int) 0x5 <<  4) // (MCI) DTOCYC x 4096
+#define 	AT91C_MCI_DTOMUL_65536                ((unsigned int) 0x6 <<  4) // (MCI) DTOCYC x 65536
+#define 	AT91C_MCI_DTOMUL_1048576              ((unsigned int) 0x7 <<  4) // (MCI) DTOCYC x 1048576
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 
+#define AT91C_MCI_SCDSEL      ((unsigned int) 0x1 <<  0) // (MCI) SD Card Selector
+#define AT91C_MCI_SCDBUS      ((unsigned int) 0x1 <<  7) // (MCI) SD Card Bus Width
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 
+#define AT91C_MCI_CMDNB       ((unsigned int) 0x1F <<  0) // (MCI) Command Number
+#define AT91C_MCI_RSPTYP      ((unsigned int) 0x3 <<  6) // (MCI) Response Type
+#define 	AT91C_MCI_RSPTYP_NO                   ((unsigned int) 0x0 <<  6) // (MCI) No response
+#define 	AT91C_MCI_RSPTYP_48                   ((unsigned int) 0x1 <<  6) // (MCI) 48-bit response
+#define 	AT91C_MCI_RSPTYP_136                  ((unsigned int) 0x2 <<  6) // (MCI) 136-bit response
+#define AT91C_MCI_SPCMD       ((unsigned int) 0x7 <<  8) // (MCI) Special CMD
+#define 	AT91C_MCI_SPCMD_NONE                 ((unsigned int) 0x0 <<  8) // (MCI) Not a special CMD
+#define 	AT91C_MCI_SPCMD_INIT                 ((unsigned int) 0x1 <<  8) // (MCI) Initialization CMD
+#define 	AT91C_MCI_SPCMD_SYNC                 ((unsigned int) 0x2 <<  8) // (MCI) Synchronized CMD
+#define 	AT91C_MCI_SPCMD_IT_CMD               ((unsigned int) 0x4 <<  8) // (MCI) Interrupt command
+#define 	AT91C_MCI_SPCMD_IT_REP               ((unsigned int) 0x5 <<  8) // (MCI) Interrupt response
+#define AT91C_MCI_OPDCMD      ((unsigned int) 0x1 << 11) // (MCI) Open Drain Command
+#define AT91C_MCI_MAXLAT      ((unsigned int) 0x1 << 12) // (MCI) Maximum Latency for Command to respond
+#define AT91C_MCI_TRCMD       ((unsigned int) 0x3 << 16) // (MCI) Transfer CMD
+#define 	AT91C_MCI_TRCMD_NO                   ((unsigned int) 0x0 << 16) // (MCI) No transfer
+#define 	AT91C_MCI_TRCMD_START                ((unsigned int) 0x1 << 16) // (MCI) Start transfer
+#define 	AT91C_MCI_TRCMD_STOP                 ((unsigned int) 0x2 << 16) // (MCI) Stop transfer
+#define AT91C_MCI_TRDIR       ((unsigned int) 0x1 << 18) // (MCI) Transfer Direction
+#define AT91C_MCI_TRTYP       ((unsigned int) 0x3 << 19) // (MCI) Transfer Type
+#define 	AT91C_MCI_TRTYP_BLOCK                ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type
+#define 	AT91C_MCI_TRTYP_MULTIPLE             ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type
+#define 	AT91C_MCI_TRTYP_STREAM               ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 
+#define AT91C_MCI_CMDRDY      ((unsigned int) 0x1 <<  0) // (MCI) Command Ready flag
+#define AT91C_MCI_RXRDY       ((unsigned int) 0x1 <<  1) // (MCI) RX Ready flag
+#define AT91C_MCI_TXRDY       ((unsigned int) 0x1 <<  2) // (MCI) TX Ready flag
+#define AT91C_MCI_BLKE        ((unsigned int) 0x1 <<  3) // (MCI) Data Block Transfer Ended flag
+#define AT91C_MCI_DTIP        ((unsigned int) 0x1 <<  4) // (MCI) Data Transfer in Progress flag
+#define AT91C_MCI_NOTBUSY     ((unsigned int) 0x1 <<  5) // (MCI) Data Line Not Busy flag
+#define AT91C_MCI_ENDRX       ((unsigned int) 0x1 <<  6) // (MCI) End of RX Buffer flag
+#define AT91C_MCI_ENDTX       ((unsigned int) 0x1 <<  7) // (MCI) End of TX Buffer flag
+#define AT91C_MCI_RXBUFF      ((unsigned int) 0x1 << 14) // (MCI) RX Buffer Full flag
+#define AT91C_MCI_TXBUFE      ((unsigned int) 0x1 << 15) // (MCI) TX Buffer Empty flag
+#define AT91C_MCI_RINDE       ((unsigned int) 0x1 << 16) // (MCI) Response Index Error flag
+#define AT91C_MCI_RDIRE       ((unsigned int) 0x1 << 17) // (MCI) Response Direction Error flag
+#define AT91C_MCI_RCRCE       ((unsigned int) 0x1 << 18) // (MCI) Response CRC Error flag
+#define AT91C_MCI_RENDE       ((unsigned int) 0x1 << 19) // (MCI) Response End Bit Error flag
+#define AT91C_MCI_RTOE        ((unsigned int) 0x1 << 20) // (MCI) Response Time-out Error flag
+#define AT91C_MCI_DCRCE       ((unsigned int) 0x1 << 21) // (MCI) data CRC Error flag
+#define AT91C_MCI_DTOE        ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag
+#define AT91C_MCI_OVRE        ((unsigned int) 0x1 << 30) // (MCI) Overrun flag
+#define AT91C_MCI_UNRE        ((unsigned int) 0x1 << 31) // (MCI) Underrun flag
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_SPI.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_SPI.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_SPI.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_SPI.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,123 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 / SPI definitions
+// Generated           : AT91 SW Application Group  12/03/2002 (10:48:02)
+//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_SPI_H
+#define AT91RM9200_SPI_H
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	//
+	AT91_REG	 SPI_CSR0; 	// Chip Select Register 0
+	AT91_REG	 SPI_CSR1; 	// Chip Select Register 1
+	AT91_REG	 SPI_CSR2; 	// Chip Select Register 2
+	AT91_REG	 SPI_CSR3; 	// Chip Select Register 3
+	AT91_REG	 Reserved1[48]; 	//
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+#endif
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN       ( 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ( 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ( 0x1 <<  7) // (SPI) SPI Software reset
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR        ( 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ( 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ( 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ( 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ( 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_DIV32       ( 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ( 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ( 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ( 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ( 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD          ( 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ( 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD          ( 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ( 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF        ( 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ( 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ( 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ( 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_SPENDRX     ( 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_SPENDTX     ( 0x1 <<  5) // (SPI) End of Transmit Transfer
+#define AT91C_SPI_RXBUFF      ( 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ( 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_SPIENS      ( 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL        ( 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ( 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_BITS        ( 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ( 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ( 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ( 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ( 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ( 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ( 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ( 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ( 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ( 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ( 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ( 0xFF << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT      ( 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_SSC.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_SSC.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_SSC.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_SSC.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,148 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 / SSC definitions
+// Generated           : AT91 SW Application Group  12/03/2002 (10:48:02)
+// 
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_SSC_H
+#define AT91RM9200_SSC_H
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 SSC_RC0R; 	// Receive Compare 0 Register
+	AT91_REG	 SSC_RC1R; 	// Receive Compare 1 Register
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+#endif
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ( 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ( 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ( 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ( 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ( 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ( 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ( 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ( 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ( 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ( 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ( 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ( 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ( 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ( 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG         ( 0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
+#define 	AT91C_SSC_CKG_NONE                 ( 0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define 	AT91C_SSC_CKG_LOW                  ( 0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define 	AT91C_SSC_CKG_HIGH                 ( 0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START       ( 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ( 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ( 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ( 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ( 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ( 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ( 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ( 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ( 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ( 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STOP        ( 0x1 << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTOUT      ( 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
+#define AT91C_SSC_STTDLY      ( 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ( 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ( 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ( 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ( 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ( 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ( 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ( 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ( 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ( 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ( 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ( 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ( 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ( 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ( 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ( 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ( 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ( 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ( 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ( 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ( 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ( 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ( 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ( 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ( 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0         ( 0x1 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_CP1         ( 0x1 <<  9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN       ( 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ( 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ( 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ( 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_SYS.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_SYS.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_SYS.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_SYS.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,738 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 definitions
+// Generated           : AT91 SW Application Group  04/16/2003 (12:30:06)
+//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_SYS_H
+#define AT91RM9200_SYS_H
+
+#ifndef __ASSEMBLY__
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	//
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	//
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	//
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	//
+	AT91_REG	 DBGU_C1R; 	// Chip ID1 Register
+	AT91_REG	 DBGU_C2R; 	// Chip ID2 Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	//
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	//
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	//
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	//
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	//
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	//
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pad Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	//
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	//
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	//
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	//
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	//
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	//
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	//
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pad Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	//
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	//
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[85]; 	//
+	AT91_REG	 PIOC_PER; 	// PIO Enable Register
+	AT91_REG	 PIOC_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOC_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved20[1]; 	//
+	AT91_REG	 PIOC_OER; 	// Output Enable Register
+	AT91_REG	 PIOC_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOC_OSR; 	// Output Status Register
+	AT91_REG	 Reserved21[1]; 	//
+	AT91_REG	 PIOC_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOC_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOC_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved22[1]; 	//
+	AT91_REG	 PIOC_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOC_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOC_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOC_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOC_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOC_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOC_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOC_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved23[1]; 	//
+	AT91_REG	 PIOC_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOC_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOC_PPUSR; 	// Pad Pull-up Status Register
+	AT91_REG	 Reserved24[1]; 	//
+	AT91_REG	 PIOC_ASR; 	// Select A Register
+	AT91_REG	 PIOC_BSR; 	// Select B Register
+	AT91_REG	 PIOC_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved25[9]; 	//
+	AT91_REG	 PIOC_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOC_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOC_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved26[85]; 	//
+	AT91_REG	 PIOD_PER; 	// PIO Enable Register
+	AT91_REG	 PIOD_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOD_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved27[1]; 	//
+	AT91_REG	 PIOD_OER; 	// Output Enable Register
+	AT91_REG	 PIOD_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOD_OSR; 	// Output Status Register
+	AT91_REG	 Reserved28[1]; 	//
+	AT91_REG	 PIOD_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOD_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOD_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved29[1]; 	//
+	AT91_REG	 PIOD_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOD_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOD_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOD_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOD_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOD_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOD_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOD_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOD_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOD_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOD_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved30[1]; 	//
+	AT91_REG	 PIOD_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOD_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOD_PPUSR; 	// Pad Pull-up Status Register
+	AT91_REG	 Reserved31[1]; 	//
+	AT91_REG	 PIOD_ASR; 	// Select A Register
+	AT91_REG	 PIOD_BSR; 	// Select B Register
+	AT91_REG	 PIOD_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved32[9]; 	//
+	AT91_REG	 PIOD_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOD_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOD_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved33[85]; 	//
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved34[1]; 	//
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved35[1]; 	//
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 CKGR_PLLAR; 	// PLL A Register
+	AT91_REG	 CKGR_PLLBR; 	// PLL B Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved36[3]; 	//
+	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved37[36]; 	//
+	AT91_REG	 ST_CR; 	// Control Register
+	AT91_REG	 ST_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 ST_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 ST_RTMR; 	// Real-time Mode Register
+	AT91_REG	 ST_SR; 	// Status Register
+	AT91_REG	 ST_IER; 	// Interrupt Enable Register
+	AT91_REG	 ST_IDR; 	// Interrupt Disable Register
+	AT91_REG	 ST_IMR; 	// Interrupt Mask Register
+	AT91_REG	 ST_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 ST_CRTR; 	// Current Real-time Register
+	AT91_REG	 Reserved38[54]; 	//
+	AT91_REG	 RTC_CR; 	// Control Register
+	AT91_REG	 RTC_MR; 	// Mode Register
+	AT91_REG	 RTC_TIMR; 	// Time Register
+	AT91_REG	 RTC_CALR; 	// Calendar Register
+	AT91_REG	 RTC_TIMALR; 	// Time Alarm Register
+	AT91_REG	 RTC_CALALR; 	// Calendar Alarm Register
+	AT91_REG	 RTC_SR; 	// Status Register
+	AT91_REG	 RTC_SCCR; 	// Status Clear Command Register
+	AT91_REG	 RTC_IER; 	// Interrupt Enable Register
+	AT91_REG	 RTC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 RTC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 RTC_VER; 	// Valid Entry Register
+	AT91_REG	 Reserved39[52]; 	//
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved40[1]; 	//
+	AT91_REG	 MC_PUIA[16]; 	// MC Protection Unit Area
+	AT91_REG	 MC_PUP; 	// MC Protection Unit Peripherals
+	AT91_REG	 MC_PUER; 	// MC Protection Unit Enable Register
+	AT91_REG	 Reserved41[2]; 	//
+	AT91_REG	 EBI_CSA; 	// Chip Select Assignment Register
+	AT91_REG	 EBI_CFGR; 	// Configuration Register
+	AT91_REG	 Reserved42[2]; 	//
+	AT91_REG	 EBI_SMC2_CSR[8]; 	// SMC2 Chip Select Register
+	AT91_REG	 EBI_SDRC_MR; 	// SDRAM Controller Mode Register
+	AT91_REG	 EBI_SDRC_TR; 	// SDRAM Controller Refresh Timer Register
+	AT91_REG	 EBI_SDRC_CR; 	// SDRAM Controller Configuration Register
+	AT91_REG	 EBI_SDRC_SRR; 	// SDRAM Controller Self Refresh Register
+	AT91_REG	 EBI_SDRC_LPR; 	// SDRAM Controller Low Power Register
+	AT91_REG	 EBI_SDRC_IER; 	// SDRAM Controller Interrupt Enable Register
+	AT91_REG	 EBI_SDRC_IDR; 	// SDRAM Controller Interrupt Disable Register
+	AT91_REG	 EBI_SDRC_IMR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 EBI_SDRC_ISR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 Reserved43[3]; 	//
+	AT91_REG	 EBI_BFC_MR; 	// BFC Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+#else
+
+/* Offsets from AT91C_BASE_SYS */
+#define AIC_SMR		(0) // Source Mode Register
+#define AIC_SVR		(128) // Source Vector Register
+#define AIC_IVR		(256) // IRQ Vector Register
+#define AIC_FVR		(260) // FIQ Vector Register
+#define AIC_ISR		(264) // Interrupt Status Register
+#define AIC_IPR		(268) // Interrupt Pending Register
+#define AIC_IMR		(272) // Interrupt Mask Register
+#define AIC_CISR	(276) // Core Interrupt Status Register
+#define AIC_IECR	(288) // Interrupt Enable Command Register
+#define AIC_IDCR	(292) // Interrupt Disable Command Register
+#define AIC_ICCR	(296) // Interrupt Clear Command Register
+#define AIC_ISCR	(300) // Interrupt Set Command Register
+#define AIC_EOICR	(304) // End of Interrupt Command Register
+#define AIC_SPU		(308) // Spurious Vector Register
+#define AIC_DCR		(312) // Debug Control Register (Protect)
+#define AIC_FFER	(320) // Fast Forcing Enable Register
+#define AIC_FFDR	(324) // Fast Forcing Disable Register
+#define AIC_FFSR	(328) // Fast Forcing Status Register
+
+/* Offsets from AT91C_BASE_SYS */
+#define DBGU_CR		(0x200 + 0) // Control Register
+#define DBGU_MR		(0x200 + 4) // Mode Register
+#define DBGU_IER	(0x200 + 8) // Interrupt Enable Register
+#define DBGU_IDR	(0x200 + 12) // Interrupt Disable Register
+#define DBGU_IMR	(0x200 + 16) // Interrupt Mask Register
+#define DBGU_CSR	(0x200 + 20) // Channel Status Register
+#define DBGU_RHR	(0x200 + 24) // Receiver Holding Register
+#define DBGU_THR	(0x200 + 28) // Transmitter Holding Register
+#define DBGU_BRGR	(0x200 + 32) // Baud Rate Generator Register
+#define DBGU_C1R	(0x200 + 64) // Chip ID1 Register
+#define DBGU_C2R	(0x200 + 68) // Chip ID2 Register
+#define DBGU_FNTR	(0x200 + 72) // Force NTRST Register
+#define DBGU_RPR	(0x200 + 256) // Receive Pointer Register
+#define DBGU_RCR	(0x200 + 260) // Receive Counter Register
+#define DBGU_TPR	(0x200 + 264) // Transmit Pointer Register
+#define DBGU_TCR	(0x200 + 268) // Transmit Counter Register
+#define DBGU_RNPR	(0x200 + 272) // Receive Next Pointer Register
+#define DBGU_RNCR	(0x200 + 276) // Receive Next Counter Register
+#define DBGU_TNPR	(0x200 + 280) // Transmit Next Pointer Register
+#define DBGU_TNCR	(0x200 + 284) // Transmit Next Counter Register
+#define DBGU_PTCR	(0x200 + 288) // PDC Transfer Control Register
+#define DBGU_PTSR	(0x200 + 292) // PDC Transfer Status Register
+
+#endif // __ASSEMBLY
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB          (0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD       (0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       (0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_MPU          (0x1 <<  2) // (MC) Memory protection Unit Abort Status
+#define AT91C_MC_ABTSZ        (0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       (0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
+#define AT91C_MC_PROT         (0x3 <<  0) // (MC) Protection
+#define 	AT91C_MC_PROT_PNAUNA               (0x0) // (MC) Privilege: No Access, User: No Access
+#define 	AT91C_MC_PROT_PRWUNA               (0x1) // (MC) Privilege: Read/Write, User: No Access
+#define 	AT91C_MC_PROT_PRWURO               (0x2) // (MC) Privilege: Read/Write, User: Read Only
+#define 	AT91C_MC_PROT_PRWURW               (0x3) // (MC) Privilege: Read/Write, User: Read/Write
+#define AT91C_MC_SIZE         (0xF <<  4) // (MC) Internal Area Size
+#define 	AT91C_MC_SIZE_1KB                  (0x0 <<  4) // (MC) Area size 1KByte
+#define 	AT91C_MC_SIZE_2KB                  (0x1 <<  4) // (MC) Area size 2KByte
+#define 	AT91C_MC_SIZE_4KB                  (0x2 <<  4) // (MC) Area size 4KByte
+#define 	AT91C_MC_SIZE_8KB                  (0x3 <<  4) // (MC) Area size 8KByte
+#define 	AT91C_MC_SIZE_16KB                 (0x4 <<  4) // (MC) Area size 16KByte
+#define 	AT91C_MC_SIZE_32KB                 (0x5 <<  4) // (MC) Area size 32KByte
+#define 	AT91C_MC_SIZE_64KB                 (0x6 <<  4) // (MC) Area size 64KByte
+#define 	AT91C_MC_SIZE_128KB                (0x7 <<  4) // (MC) Area size 128KByte
+#define 	AT91C_MC_SIZE_256KB                (0x8 <<  4) // (MC) Area size 256KByte
+#define 	AT91C_MC_SIZE_512KB                (0x9 <<  4) // (MC) Area size 512KByte
+#define 	AT91C_MC_SIZE_1MB                  (0xA <<  4) // (MC) Area size 1MByte
+#define 	AT91C_MC_SIZE_2MB                  (0xB <<  4) // (MC) Area size 2MByte
+#define 	AT91C_MC_SIZE_4MB                  (0xC <<  4) // (MC) Area size 4MByte
+#define 	AT91C_MC_SIZE_8MB                  (0xD <<  4) // (MC) Area size 8MByte
+#define 	AT91C_MC_SIZE_16MB                 (0xE <<  4) // (MC) Area size 16MByte
+#define 	AT91C_MC_SIZE_64MB                 (0xF <<  4) // (MC) Area size 64MByte
+#define AT91C_MC_BA           (0x3FFFF << 10) // (MC) Internal Area Base Address
+// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
+// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
+#define AT91C_MC_PUEB         (0x1 <<  0) // (MC) Protection Unit enable Bit
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface
+// *****************************************************************************
+// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register --------
+#define AT91C_RTC_UPDTIM      (0x1 <<  0) // (RTC) Update Request Time Register
+#define AT91C_RTC_UPDCAL      (0x1 <<  1) // (RTC) Update Request Calendar Register
+#define AT91C_RTC_TIMEVSEL    (0x3 <<  8) // (RTC) Time Event Selection
+#define 	AT91C_RTC_TIMEVSEL_MINUTE               (0x0 <<  8) // (RTC) Minute change.
+#define 	AT91C_RTC_TIMEVSEL_HOUR                 (0x1 <<  8) // (RTC) Hour change.
+#define 	AT91C_RTC_TIMEVSEL_DAY24                (0x2 <<  8) // (RTC) Every day at midnight.
+#define 	AT91C_RTC_TIMEVSEL_DAY12                (0x3 <<  8) // (RTC) Every day at noon.
+#define AT91C_RTC_CALEVSEL    (0x3 << 16) // (RTC) Calendar Event Selection
+#define 	AT91C_RTC_CALEVSEL_WEEK                 (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).
+#define 	AT91C_RTC_CALEVSEL_MONTH                (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).
+#define 	AT91C_RTC_CALEVSEL_YEAR                 (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).
+// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register --------
+#define AT91C_RTC_HRMOD       (0x1 <<  0) // (RTC) 12-24 hour Mode
+// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register --------
+#define AT91C_RTC_SEC         (0x7F <<  0) // (RTC) Current Second
+#define AT91C_RTC_MIN         (0x7F <<  8) // (RTC) Current Minute
+#define AT91C_RTC_HOUR        (0x3F << 16) // (RTC) Current Hour
+#define AT91C_RTC_AMPM        (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator
+// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register --------
+#define AT91C_RTC_CENT        (0x3F <<  0) // (RTC) Current Century
+#define AT91C_RTC_YEAR        (0xFF <<  8) // (RTC) Current Year
+#define AT91C_RTC_MONTH       (0x1F << 16) // (RTC) Current Month
+#define AT91C_RTC_DAY         (0x7 << 21) // (RTC) Current Day
+#define AT91C_RTC_DATE        (0x3F << 24) // (RTC) Current Date
+// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register --------
+#define AT91C_RTC_SECEN       (0x1 <<  7) // (RTC) Second Alarm Enable
+#define AT91C_RTC_MINEN       (0x1 << 15) // (RTC) Minute Alarm
+#define AT91C_RTC_HOUREN      (0x1 << 23) // (RTC) Current Hour
+// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register --------
+#define AT91C_RTC_MONTHEN     (0x1 << 23) // (RTC) Month Alarm Enable
+#define AT91C_RTC_DATEEN      (0x1 << 31) // (RTC) Date Alarm Enable
+// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register --------
+#define AT91C_RTC_ACKUPD      (0x1 <<  0) // (RTC) Acknowledge for Update
+#define AT91C_RTC_ALARM       (0x1 <<  1) // (RTC) Alarm Flag
+#define AT91C_RTC_SECEV       (0x1 <<  2) // (RTC) Second Event
+#define AT91C_RTC_TIMEV       (0x1 <<  3) // (RTC) Time Event
+#define AT91C_RTC_CALEV       (0x1 <<  4) // (RTC) Calendar event
+// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register --------
+// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register --------
+// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register --------
+// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register --------
+// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register --------
+#define AT91C_RTC_NVTIM       (0x1 <<  0) // (RTC) Non valid Time
+#define AT91C_RTC_NVCAL       (0x1 <<  1) // (RTC) Non valid Calendar
+#define AT91C_RTC_NVTIMALR    (0x1 <<  2) // (RTC) Non valid time Alarm
+#define AT91C_RTC_NVCALALR    (0x1 <<  3) // (RTC) Nonvalid Calendar Alarm
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Timer Interface
+// *****************************************************************************
+// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register --------
+#define AT91C_ST_WDRST        (0x1 <<  0) // (ST) Watchdog Timer Restart
+// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register --------
+#define AT91C_ST_PIV          (0xFFFF <<  0) // (ST) Watchdog Timer Restart
+// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register --------
+#define AT91C_ST_WDV          (0xFFFF <<  0) // (ST) Watchdog Timer Restart
+#define AT91C_ST_RSTEN        (0x1 << 16) // (ST) Reset Enable
+#define AT91C_ST_EXTEN        (0x1 << 17) // (ST) External Signal Assertion Enable
+// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register --------
+#define AT91C_ST_RTPRES       (0xFFFF <<  0) // (ST) Real-time Timer Prescaler Value
+// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register --------
+#define AT91C_ST_PITS         (0x1 <<  0) // (ST) Period Interval Timer Interrupt
+#define AT91C_ST_WDOVF        (0x1 <<  1) // (ST) Watchdog Overflow
+#define AT91C_ST_RTTINC       (0x1 <<  2) // (ST) Real-time Timer Increment
+#define AT91C_ST_ALMS         (0x1 <<  3) // (ST) Alarm Status
+// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register --------
+// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register --------
+// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register --------
+// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register --------
+#define AT91C_ST_ALMV         (0xFFFFF <<  0) // (ST) Alarm Value Value
+// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register --------
+#define AT91C_ST_CRTV         (0xFFFFF <<  0) // (ST) Current Real-time Value
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         (0x1 <<  1) // (PMC) USB Device Port Clock
+#define AT91C_PMC_MCKUDP      (0x1 <<  2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend
+#define AT91C_PMC_UHP         (0x1 <<  4) // (PMC) USB Host Port Clock
+#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        (0x1 << 11) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK4        (0x1 << 12) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK5        (0x1 << 13) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK6        (0x1 << 14) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK7        (0x1 << 15) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLLA_CLK             (0x2) // (PMC) Clock from PLL A is selected
+#define 	AT91C_PMC_CSS_PLLB_CLK             (0x3) // (PMC) Clock from PLL B is selected
+#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+#define AT91C_PMC_MDIV        (0x3 <<  8) // (PMC) Master Clock Division
+#define 	AT91C_PMC_MDIV_1                    (0x0 <<  8) // (PMC) The master clock and the processor clock are the same
+#define 	AT91C_PMC_MDIV_2                    (0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock
+#define 	AT91C_PMC_MDIV_3                    (0x2 <<  8) // (PMC) The processor clock is three times faster than the master clock
+#define 	AT91C_PMC_MDIV_4                    (0x3 <<  8) // (PMC) The processor clock is four times faster than the master clock
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKA       (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKB       (0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK4RDY     (0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK5RDY     (0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK6RDY     (0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK7RDY     (0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCTEST    (0x1 <<  1) // (CKGR) Oscillator Test
+#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
+#define AT91C_CKGR_DIVA       (0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIVA_0                    (0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIVA_BYPASS               (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLACOUNT  (0x3F <<  8) // (CKGR) PLL A Counter
+#define AT91C_CKGR_OUTA       (0x3 << 14) // (CKGR) PLL A Output Frequency Range
+#define 	AT91C_CKGR_OUTA_0                    (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_1                    (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_2                    (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_3                    (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_MULA       (0x7FF << 16) // (CKGR) PLL A Multiplier
+#define AT91C_CKGR_SRCA       (0x1 << 29) // (CKGR) PLL A Source
+// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIVB       (0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIVB_0                    (0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIVB_BYPASS               (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLBCOUNT  (0x3F <<  8) // (CKGR) PLL B Counter
+#define AT91C_CKGR_OUTB       (0x3 << 14) // (CKGR) PLL B Output Frequency Range
+#define 	AT91C_CKGR_OUTB_0                    (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_1                    (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_2                    (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_3                    (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_MULB       (0x7FF << 16) // (CKGR) PLL B Multiplier
+#define AT91C_CKGR_USB_96M    (0x1 << 28) // (CKGR) Divider for USB Ports
+#define AT91C_CKGR_USB_PLL    (0x1 << 29) // (CKGR) PLL Use
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_DBGU_TXRDY	(0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_DBGU_TXEMPTY	(0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_DBGU_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
+// *****************************************************************************
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR External Bus Interface
+// *****************************************************************************
+// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register --------
+#define AT91C_EBI_CS0A        (0x1 <<  0) // (EBI) Chip Select 0 Assignment
+#define 	AT91C_EBI_CS0A_SMC                  (0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller.
+#define 	AT91C_EBI_CS0A_BFC                  (0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller.
+#define AT91C_EBI_CS1A        (0x1 <<  1) // (EBI) Chip Select 1 Assignment
+#define 	AT91C_EBI_CS1A_SMC                  (0x0 <<  1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller.
+#define 	AT91C_EBI_CS1A_SDRAMC               (0x1 <<  1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller.
+#define AT91C_EBI_CS3A        (0x1 <<  3) // (EBI) Chip Select 3 Assignment
+#define 	AT91C_EBI_CS3A_SMC                  (0x0 <<  3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.
+#define 	AT91C_EBI_CS3A_SMC_SmartMedia       (0x1 <<  3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
+#define AT91C_EBI_CS4A        (0x1 <<  4) // (EBI) Chip Select 4 Assignment
+#define 	AT91C_EBI_CS4A_SMC                  (0x0 <<  4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.
+#define 	AT91C_EBI_CS4A_SMC_CompactFlash     (0x1 <<  4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.
+// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register --------
+#define AT91C_EBI_DBPUC       (0x1 <<  0) // (EBI) Data Bus Pull-Up Configuration
+#define AT91C_EBI_EBSEN       (0x1 <<  1) // (EBI) Bus Sharing Enable
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface
+// *****************************************************************************
+
+// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register --------
+#define AT91C_SMC2_NWS        (0x7F <<  0) // (SMC2) Number of Wait States
+#define AT91C_SMC2_WSEN       (0x1 <<  7) // (SMC2) Wait State Enable
+#define AT91C_SMC2_TDF        (0xF <<  8) // (SMC2) Data Float Time
+#define AT91C_SMC2_BAT        (0x1 << 12) // (SMC2) Byte Access Type
+#define AT91C_SMC2_DBW        (0x1 << 13) // (SMC2) Data Bus Width
+#define 	AT91C_SMC2_DBW_16                   (0x1 << 13) // (SMC2) 16-bit.
+#define 	AT91C_SMC2_DBW_8                    (0x2 << 13) // (SMC2) 8-bit.
+#define AT91C_SMC2_DRP        (0x1 << 15) // (SMC2) Data Read Protocol
+#define AT91C_SMC2_ACSS       (0x3 << 16) // (SMC2) Address to Chip Select Setup
+#define 	AT91C_SMC2_ACSS_STANDARD             (0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.
+#define 	AT91C_SMC2_ACSS_1_CYCLE              (0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access.
+#define 	AT91C_SMC2_ACSS_2_CYCLES             (0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access.
+#define 	AT91C_SMC2_ACSS_3_CYCLES             (0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access.
+#define AT91C_SMC2_RWSETUP    (0x7 << 24) // (SMC2) Read and Write Signal Setup Time
+#define AT91C_SMC2_RWHOLD     (0x7 << 29) // (SMC2) Read and Write Signal Hold Time
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface
+// *****************************************************************************
+// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register --------
+#define AT91C_SDRC_MODE       (0xF <<  0) // (SDRC) Mode
+#define 	AT91C_SDRC_MODE_NORMAL_CMD           (0x0) // (SDRC) Normal Mode
+#define 	AT91C_SDRC_MODE_NOP_CMD              (0x1) // (SDRC) NOP Command
+#define 	AT91C_SDRC_MODE_PRCGALL_CMD          (0x2) // (SDRC) All Banks Precharge Command
+#define 	AT91C_SDRC_MODE_LMR_CMD              (0x3) // (SDRC) Load Mode Register Command
+#define 	AT91C_SDRC_MODE_RFSH_CMD             (0x4) // (SDRC) Refresh Command
+#define AT91C_SDRC_DBW        (0x1 <<  4) // (SDRC) Data Bus Width
+#define 	AT91C_SDRC_DBW_32_BITS              (0x0 <<  4) // (SDRC) 32 Bits datas bus
+#define 	AT91C_SDRC_DBW_16_BITS              (0x1 <<  4) // (SDRC) 16 Bits datas bus
+// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register --------
+#define AT91C_SDRC_COUNT      (0xFFF <<  0) // (SDRC) Refresh Counter
+// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register --------
+#define AT91C_SDRC_NC         (0x3 <<  0) // (SDRC) Number of Column Bits
+#define 	AT91C_SDRC_NC_8                    (0x0) // (SDRC) 8 Bits
+#define 	AT91C_SDRC_NC_9                    (0x1) // (SDRC) 9 Bits
+#define 	AT91C_SDRC_NC_10                   (0x2) // (SDRC) 10 Bits
+#define 	AT91C_SDRC_NC_11                   (0x3) // (SDRC) 11 Bits
+#define AT91C_SDRC_NR         (0x3 <<  2) // (SDRC) Number of Row Bits
+#define 	AT91C_SDRC_NR_11                   (0x0 <<  2) // (SDRC) 11 Bits
+#define 	AT91C_SDRC_NR_12                   (0x1 <<  2) // (SDRC) 12 Bits
+#define 	AT91C_SDRC_NR_13                   (0x2 <<  2) // (SDRC) 13 Bits
+#define AT91C_SDRC_NB         (0x1 <<  4) // (SDRC) Number of Banks
+#define 	AT91C_SDRC_NB_2_BANKS              (0x0 <<  4) // (SDRC) 2 banks
+#define 	AT91C_SDRC_NB_4_BANKS              (0x1 <<  4) // (SDRC) 4 banks
+#define AT91C_SDRC_CAS        (0x3 <<  5) // (SDRC) CAS Latency
+#define 	AT91C_SDRC_CAS_2                    (0x2 <<  5) // (SDRC) 2 cycles
+#define AT91C_SDRC_TWR        (0xF <<  7) // (SDRC) Number of Write Recovery Time Cycles
+#define AT91C_SDRC_TRC        (0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles
+#define AT91C_SDRC_TRP        (0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles
+#define AT91C_SDRC_TRCD       (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles
+#define AT91C_SDRC_TRAS       (0xF << 23) // (SDRC) Number of RAS Active Time Cycles
+#define AT91C_SDRC_TXSR       (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles
+// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register --------
+#define AT91C_SDRC_SRCB       (0x1 <<  0) // (SDRC) Self-refresh Command Bit
+// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register --------
+#define AT91C_SDRC_LPCB       (0x1 <<  0) // (SDRC) Low-power Command Bit
+// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
+#define AT91C_SDRC_RES        (0x1 <<  0) // (SDRC) Refresh Error Status
+// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
+// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
+// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Burst Flash Controller Interface
+// *****************************************************************************
+// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register --------
+#define AT91C_BFC_BFCOM       (0x3 <<  0) // (BFC) Burst Flash Controller Operating Mode
+#define 	AT91C_BFC_BFCOM_DISABLED             (0x0) // (BFC) NPCS0 is driven by the SMC or remains high.
+#define 	AT91C_BFC_BFCOM_ASYNC                (0x1) // (BFC) Asynchronous
+#define 	AT91C_BFC_BFCOM_BURST_READ           (0x2) // (BFC) Burst Read
+#define AT91C_BFC_BFCC        (0x3 <<  2) // (BFC) Burst Flash Controller Operating Mode
+#define 	AT91C_BFC_BFCC_MCK                  (0x1 <<  2) // (BFC) Master Clock.
+#define 	AT91C_BFC_BFCC_MCK_DIV_2            (0x2 <<  2) // (BFC) Master Clock divided by 2.
+#define 	AT91C_BFC_BFCC_MCK_DIV_4            (0x3 <<  2) // (BFC) Master Clock divided by 4.
+#define AT91C_BFC_AVL         (0xF <<  4) // (BFC) Address Valid Latency
+#define AT91C_BFC_PAGES       (0x7 <<  8) // (BFC) Page Size
+#define 	AT91C_BFC_PAGES_NO_PAGE              (0x0 <<  8) // (BFC) No page handling.
+#define 	AT91C_BFC_PAGES_16                   (0x1 <<  8) // (BFC) 16 bytes page size.
+#define 	AT91C_BFC_PAGES_32                   (0x2 <<  8) // (BFC) 32 bytes page size.
+#define 	AT91C_BFC_PAGES_64                   (0x3 <<  8) // (BFC) 64 bytes page size.
+#define 	AT91C_BFC_PAGES_128                  (0x4 <<  8) // (BFC) 128 bytes page size.
+#define 	AT91C_BFC_PAGES_256                  (0x5 <<  8) // (BFC) 256 bytes page size.
+#define 	AT91C_BFC_PAGES_512                  (0x6 <<  8) // (BFC) 512 bytes page size.
+#define 	AT91C_BFC_PAGES_1024                 (0x7 <<  8) // (BFC) 1024 bytes page size.
+#define AT91C_BFC_OEL         (0x3 << 12) // (BFC) Output Enable Latency
+#define AT91C_BFC_BAAEN       (0x1 << 16) // (BFC) Burst Address Advance Enable
+#define AT91C_BFC_BFOEH       (0x1 << 17) // (BFC) Burst Flash Output Enable Handling
+#define AT91C_BFC_MUXEN       (0x1 << 18) // (BFC) Multiplexed Bus Enable
+#define AT91C_BFC_RDYEN       (0x1 << 19) // (BFC) Ready Enable Mode
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_TC.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_TC.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_TC.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_TC.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,184 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 definitions
+// Generated           : AT91 SW Application Group  12/03/2002 (10:48:02)
+// 
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_TC_H
+#define AT91RM9200_TC_H
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+#endif
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ( 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ( 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ( 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_TCCLKS       ( 0x7 <<  0) // (TC) Clock Selection
+#define		AT91C_TC_TIMER_DIV1_CLOCK             ( 0x0 <<  0) // (TC) MCK/2
+#define		AT91C_TC_TIMER_DIV2_CLOCK             ( 0x1 <<  0) // (TC) MCK/8
+#define		AT91C_TC_TIMER_DIV3_CLOCK             ( 0x2 <<  0) // (TC) MCK/32
+#define		AT91C_TC_TIMER_DIV4_CLOCK             ( 0x3 <<  0) // (TC) MCK/128
+#define		AT91C_TC_TIMER_DIV5_CLOCK             ( 0x4 <<  0) // (TC) MCK/256 = SLOW CLOCK
+#define		AT91C_TC_TIMER_XC0                    ( 0x5 <<  0) // (TC) XC0
+#define		AT91C_TC_TIMER_XC1                    ( 0x6 <<  0) // (TC) XC1
+#define		AT91C_TC_TIMER_XC2                    ( 0x7 <<  0) // (TC) XC2
+#define	AT91C_TC_CLKI         ( 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ( 0x3 <<  4) // (TC) Burst Signal Selection
+#define AT91C_TC_CPCSTOP      ( 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_CPCDIS       ( 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_EEVTEDG      ( 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ( 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ( 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ( 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ( 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ( 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_NONE                 ( 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_RISING               ( 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_FALLING              ( 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_BOTH                 ( 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ENETRG       ( 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ( 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ( 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ( 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ( 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ( 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ( 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ( 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ( 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ( 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ( 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ( 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ( 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_ACPC         ( 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ( 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ( 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ( 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ( 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_AEEVT        ( 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ( 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ( 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ( 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ( 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ( 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ( 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ( 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ( 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ( 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ( 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ( 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ( 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ( 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ( 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ( 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ( 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ( 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ( 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ( 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ( 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ( 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ( 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ( 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ( 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ( 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ( 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ( 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ( 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ( 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ( 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ( 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ( 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ( 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ( 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ( 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ( 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRCS        ( 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_ETRGS        ( 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ( 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ( 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ( 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ( 0x1 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ( 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ( 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ( 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ( 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ( 0x1 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ( 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ( 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ( 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ( 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ( 0x1 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ( 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ( 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ( 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA2                ( 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_TWI.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_TWI.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_TWI.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_TWI.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,108 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 / TWI definitions
+// Generated           : AT91 SW Application Group  12/03/2002 (10:48:02)
+//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_TWI_H
+#define AT91RM9200_TWI_H
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 TWI_SMR; 	// Slave Mode Register
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved0[3]; 	//
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[50]; 	//
+	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
+	AT91_REG	 TWI_RCR; 	// Receive Counter Register
+	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
+	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
+} AT91S_TWI, *AT91PS_TWI;
+
+#endif
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START       ( 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ( 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ( 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ( 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN        ( 0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
+#define AT91C_TWI_SVDIS       ( 0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
+#define AT91C_TWI_SWRST       ( 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ      ( 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ( 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ( 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ( 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ( 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ( 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ( 0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
+#define AT91C_TWI_SADR        ( 0x7F << 16) // (TWI) Slave Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV       ( 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ( 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ( 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP      ( 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ( 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ( 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD      ( 0x1 <<  3) // (TWI) Slave Read
+#define AT91C_TWI_SVACC       ( 0x1 <<  4) // (TWI) Slave Access
+#define AT91C_TWI_GCACC       ( 0x1 <<  5) // (TWI) General Call Access
+#define AT91C_TWI_OVRE        ( 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ( 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ( 0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST      ( 0x1 <<  9) // (TWI) Arbitration Lost
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_UDP.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_UDP.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_UDP.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_UDP.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,123 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 / UDP Device definitions
+// Generated           : AT91 SW Application Group  12/03/2002 (10:48:02)
+//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_UDP_H
+#define AT91RM9200_UDP_H
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	//
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	//
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	//
+	AT91_REG	 UDP_CSR[8]; 	// Endpoint Control and Status Register
+	AT91_REG	 UDP_FDR[8]; 	// Endpoint FIFO Data Register
+} AT91S_UDP, *AT91PS_UDP;
+
+#endif
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM     ( 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ( 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ( 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN      ( 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ( 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_RMWUPE      ( 0x1 <<  2) // (UDP) Remote Wake Up Enable
+#define AT91C_UDP_RSMINPR     ( 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD        ( 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ( 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0      ( 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ( 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ( 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ( 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ( 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ( 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6      ( 0x1 <<  6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7      ( 0x1 <<  7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP      ( 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ( 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ( 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ( 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ( 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES   ( 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0         ( 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ( 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ( 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ( 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ( 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ( 0x1 <<  5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6         ( 0x1 <<  6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7         ( 0x1 <<  7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP      ( 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ( 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ( 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ( 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ( 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ( 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ( 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ( 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ( 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ( 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ( 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ( 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ( 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ( 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ( 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ( 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ( 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ( 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ( 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_UHP.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_UHP.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_UHP.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_UHP.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,70 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 / USB Host definitions
+// Generated           : AT91 SW Application Group  12/03/2002 (10:48:02)
+//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_UHP_H
+#define AT91RM9200_UHP_H
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Host Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+
+typedef struct _AT91S_UHP {
+	AT91_REG	 UHP_HcRevision; 	// Revision
+	AT91_REG	 UHP_HcControl; 	// Operating modes for the Host Controller
+	AT91_REG	 UHP_HcCommandStatus; 	// Command & status Register
+	AT91_REG	 UHP_HcInterruptStatus; 	// Interrupt Status Register
+	AT91_REG	 UHP_HcInterruptEnable; 	// Interrupt Enable Register
+	AT91_REG	 UHP_HcInterruptDisable; 	// Interrupt Disable Register
+	AT91_REG	 UHP_HcHCCA; 	// Pointer to the Host Controller Communication Area
+	AT91_REG	 UHP_HcPeriodCurrentED; 	// Current Isochronous or Interrupt Endpoint Descriptor
+	AT91_REG	 UHP_HcControlHeadED; 	// First Endpoint Descriptor of the Control list
+	AT91_REG	 UHP_HcControlCurrentED; 	// Endpoint Control and Status Register
+	AT91_REG	 UHP_HcBulkHeadED; 	// First endpoint register of the Bulk list
+	AT91_REG	 UHP_HcBulkCurrentED; 	// Current endpoint of the Bulk list
+	AT91_REG	 UHP_HcBulkDoneHead; 	// Last completed transfer descriptor
+	AT91_REG	 UHP_HcFmInterval; 	// Bit time between 2 consecutive SOFs
+	AT91_REG	 UHP_HcFmRemaining; 	// Bit time remaining in the current Frame
+	AT91_REG	 UHP_HcFmNumber; 	// Frame number
+	AT91_REG	 UHP_HcPeriodicStart; 	// Periodic Start
+	AT91_REG	 UHP_HcLSThreshold; 	// LS Threshold
+	AT91_REG	 UHP_HcRhDescriptorA; 	// Root Hub characteristics A
+	AT91_REG	 UHP_HcRhDescriptorB; 	// Root Hub characteristics B
+	AT91_REG	 UHP_HcRhStatus; 	// Root Hub Status register
+	AT91_REG	 UHP_HcRhPortStatus[2]; 	// Root Hub Port Status Register
+} AT91S_UHP, *AT91PS_UHP;
+
+#endif
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_USART.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_USART.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_USART.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/AT91RM9200_USART.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,168 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2004, Atmel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// -  Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+// -  Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the disclaimer below in the documentation and/or
+// other materials provided with the distribution.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name           : AT91RM9200.h
+// Object              : AT91RM9200 / USART definitions
+// Generated           : AT91 SW Application Group  01/17/2003 (13:41:22)
+//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_USART_H
+#define AT91RM9200_USART_H
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	//
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 US_XXR; 	// XON_XOFF Register
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved1[44]; //
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+#endif
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX        ( 0x1 <<  2) // (USART) Reset Receiver
+#define AT91C_US_RSTTX        ( 0x1 <<  3) // (USART) Reset Transmitter
+#define AT91C_US_RXEN	      ( 0x1 <<  4) // (USART) Receiver Enable
+#define AT91C_US_RXDIS        ( 0x1 <<  5) // (USART) Receiver Disable
+#define AT91C_US_TXEN	      ( 0x1 <<  6) // (USART) Transmitter Enable
+#define AT91C_US_TXDIS        ( 0x1 <<  7) // (USART) Transmitter Disable
+#define AT91C_US_RSTSTA       ( 0x1 <<  8) // (USART) Reset Status Bits
+#define AT91C_US_STTBRK       ( 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ( 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ( 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ( 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ( 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ( 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ( 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ( 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ( 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ( 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ( 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE       ( 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ( 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ( 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ( 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ( 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ( 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ( 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ( 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ( 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ( 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ( 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ( 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ( 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ( 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ( 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ( 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ( 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ( 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ( 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ( 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_PAR          ( 0x7 <<  9) // (USART) Parity type
+#define		AT91C_US_PAR_EVEN                 ( 0x0 <<  9) // (USART) Even Parity
+#define		AT91C_US_PAR_ODD                  ( 0x1 <<  9) // (USART) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ( 0x2 <<  9) // (USART) Parity forced to 0 (Space)
+#define		AT91C_US_PAR_MARK                 ( 0x3 <<  9) // (USART) Parity forced to 1 (Mark)
+#define		AT91C_US_PAR_NONE                 ( 0x4 <<  9) // (USART) No Parity
+#define		AT91C_US_PAR_MULTI_DROP           ( 0x6 <<  9) // (USART) Multi-drop mode
+#define AT91C_US_NBSTOP       ( 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ( 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ( 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ( 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_CHMODE       ( 0x3 << 14) // (USART) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ( 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ( 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ( 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ( 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin.
+#define AT91C_US_MSBF         ( 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ( 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ( 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ( 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ( 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ( 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ( 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ( 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY        ( 0x1 <<  0) // (USART) RXRDY Interrupt
+#define AT91C_US_TXRDY        ( 0x1 <<  1) // (USART) TXRDY Interrupt
+#define AT91C_US_RXBRK        ( 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_ENDRX        ( 0x1 <<  3) // (USART) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ( 0x1 <<  4) // (USART) End of Transmit Interrupt
+#define AT91C_US_OVRE         ( 0x1 <<  5) // (USART) Overrun Interrupt
+#define AT91C_US_FRAME        ( 0x1 <<  6) // (USART) Framing Error Interrupt
+#define AT91C_US_PARE         ( 0x1 <<  7) // (USART) Parity Error Interrupt
+#define AT91C_US_TIMEOUT      ( 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_TXEMPTY      ( 0x1 <<  9) // (USART) TXEMPTY Interrupt
+#define AT91C_US_ITERATION    ( 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_TXBUFE       ( 0x1 << 11) // (USART) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ( 0x1 << 12) // (USART) RXBUFF Interrupt
+#define AT91C_US_NACK         ( 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ( 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ( 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ( 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ( 0x1 << 19) // (USART) Clear To Send Input Change Flag
+#define AT91C_US_COMM_TX      ( 0x1 << 30) // (USART) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ( 0x1 << 31) // (USART) COMM_RX Interrupt
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI           ( 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ( 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ( 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ( 0x1 << 23) // (USART) Image of CTS Input
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/at91rm9200dk.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/at91rm9200dk.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/at91rm9200dk.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/at91rm9200dk.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,81 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/at91rm9200dk.h
+ *
+ *  Copyright (c) 2003 SAN People
+ *  Copyright (c) 2003 ATMEL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_AT91RM9200DK_H
+#define __ASM_ARCH_HARDWARE_AT91RM9200DK_H
+
+
+/* AT91RM92000 clocks */
+#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
+#define AT91C_MASTER_CLOCK	59904000	/* peripheral clock (AT91C_MAIN_CLOCK / 3) */
+#define AT91C_SLOW_CLOCK	32768		/* slow clock */
+#define AT91_PLLB_INIT		0x1048be0e	/* (18.432 / 14 * 73) /2 = 47.9714  */
+
+/* FLASH */
+#define AT91_FLASH_BASE		0x10000000	// NCS0: Flash physical base address
+
+/* SDRAM */
+#define AT91_SDRAM_BASE		0x20000000	// NCS1: SDRAM physical base address
+
+/* SmartMedia */
+#define AT91_SMARTMEDIA_BASE	0x40000000	// NCS3: Smartmedia physical base address
+
+/* Multi-Master Memory controller */
+#define AT91_UHP_BASE		0x00300000	// USB Host controller
+
+
+/* Peripheral interrupt configuration */
+#define AT91_SMR_FIQ	(AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (FIQ)
+#define AT91_SMR_SYS	(AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// System Peripheral
+#define AT91_SMR_PIOA	(AT91C_AIC_PRIOR_LOWEST	 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller A
+#define AT91_SMR_PIOB	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller B
+#define AT91_SMR_PIOC	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller C
+#define AT91_SMR_PIOD	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller D
+#define AT91_SMR_US0	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 0
+#define AT91_SMR_US1	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 1
+#define AT91_SMR_US2	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 2
+#define AT91_SMR_US3	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 3
+#define AT91_SMR_MCI	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Multimedia Card Interface
+#define AT91_SMR_UDP	(AT91C_AIC_PRIOR_4       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USB Device Port
+#define AT91_SMR_TWI	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Two-Wire Interface
+#define AT91_SMR_SPI	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Peripheral Interface
+#define AT91_SMR_SSC0	(AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Synchronous Controller 0
+#define AT91_SMR_SSC1	(AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Synchronous Controller 1
+#define AT91_SMR_SSC2	(AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Synchronous Controller 2
+#define AT91_SMR_TC0	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 0
+#define AT91_SMR_TC1	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 1
+#define AT91_SMR_TC2	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 2
+#define AT91_SMR_TC3	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 3
+#define AT91_SMR_TC4	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 4
+#define AT91_SMR_TC5	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 5
+#define AT91_SMR_UHP	(AT91C_AIC_PRIOR_3       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USB Host port
+#define AT91_SMR_EMAC	(AT91C_AIC_PRIOR_3       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Ethernet MAC
+#define AT91_SMR_IRQ0	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ0)
+#define AT91_SMR_IRQ1	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ1)
+#define AT91_SMR_IRQ2	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ2)
+#define AT91_SMR_IRQ3	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ3)
+#define AT91_SMR_IRQ4	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ4)
+#define AT91_SMR_IRQ5	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ5)
+#define AT91_SMR_IRQ6	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ6)
+
+#define AT91C_CONSOLE_DEFAULT_BAUDRATE 115200	/* default serial console baud-rate */
+
+/*
+ * Serial port configuration.
+ *    0 .. 3 = USART0 .. USART3
+ *    4      = DBGU
+ */
+#define AT91C_UART_MAP		{ 4, 1, -1, -1, -1 }	/* ttyS0, ..., ttyS4 */
+#define AT91C_CONSOLE		0			/* ttyS0 */
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/csb337.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/csb337.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/csb337.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/csb337.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,82 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/csb337.h
+ *
+ *  Copyright (c) 2003 Christopher Bahns & David Knickerbocker
+ *                     Polaroid Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_CSB337_H
+#define __ASM_ARCH_HARDWARE_CSB337_H
+
+
+/* AT91RM92000 clocks on CSB337 */
+#define AT91C_MAIN_CLOCK	184320000
+#define AT91C_MASTER_CLOCK	46080000	/* peripheral clock (AT91C_MAIN_CLOCK / 4) */
+#define AT91C_SLOW_CLOCK	32768		/* slow clock */
+#define AT91_PLLB_INIT		0x128a3e19	/* (3.6864 * (650+1) / 25) /2 = 47.9969 */
+
+/* FLASH */
+#define AT91_FLASH_BASE		0x10000000	// NCS0: Flash physical base address
+
+/* SDRAM */
+#define AT91_SDRAM_BASE		0x20000000	// NCS1: SDRAM physical base address
+
+/* SmartMedia */
+#define AT91_SMARTMEDIA_BASE	0x40000000	// NCS3: Smartmedia physical base address
+
+/* Multi-Master Memory controller */
+#define AT91_UHP_BASE		0x00300000	// USB Host controller
+
+
+/* Peripheral interrupt configuration */
+#define AT91_SMR_FIQ	(AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (FIQ)
+#define AT91_SMR_SYS	(AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// System Peripheral
+#define AT91_SMR_PIOA	(AT91C_AIC_PRIOR_LOWEST	 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller A
+#define AT91_SMR_PIOB	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller B
+#define AT91_SMR_PIOC	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller C
+#define AT91_SMR_PIOD	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller D
+#define AT91_SMR_US0	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 0
+#define AT91_SMR_US1	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 1
+#define AT91_SMR_US2	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 2
+#define AT91_SMR_US3	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 3
+#define AT91_SMR_MCI	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Multimedia Card Interface
+#define AT91_SMR_UDP	(AT91C_AIC_PRIOR_4       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USB Device Port
+#define AT91_SMR_TWI	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Two-Wire Interface
+#define AT91_SMR_SPI	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Peripheral Interface
+#define AT91_SMR_SSC0	(AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Synchronous Controller 0
+#define AT91_SMR_SSC1	(AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Synchronous Controller 1
+#define AT91_SMR_SSC2	(AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Synchronous Controller 2
+#define AT91_SMR_TC0	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 0
+#define AT91_SMR_TC1	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 1
+#define AT91_SMR_TC2	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 2
+#define AT91_SMR_TC3	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 3
+#define AT91_SMR_TC4	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 4
+#define AT91_SMR_TC5	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 5
+#define AT91_SMR_UHP	(AT91C_AIC_PRIOR_3       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USB Host port
+#define AT91_SMR_EMAC	(AT91C_AIC_PRIOR_3       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Ethernet MAC
+#define AT91_SMR_IRQ0	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ0)
+#define AT91_SMR_IRQ1	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ1)
+#define AT91_SMR_IRQ2	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ2)
+#define AT91_SMR_IRQ3	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ3)
+#define AT91_SMR_IRQ4	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ4)
+#define AT91_SMR_IRQ5	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ5)
+#define AT91_SMR_IRQ6	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ6)
+
+
+#define AT91C_CONSOLE_DEFAULT_BAUDRATE 38400
+
+/*
+ * Serial port configuration.
+ *    0 .. 3 = USART0 .. USART3
+ *    4      = DBGU
+ */
+#define AT91C_UART_MAP		{ 4, 1, -1, -1, -1 }	/* ttyS0, ..., ttyS4 */
+#define AT91C_CONSOLE		0			/* ttyS0 */
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/csb637.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/csb637.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/csb637.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/csb637.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,78 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/csb637.h
+ *
+ *  Copyright (c) 2005 Bill Gatliff
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_CSB637_H
+#define __ASM_ARCH_HARDWARE_CSB637_H
+
+
+/* AT91RM92000 clocks on CSB637 */
+#define AT91C_MAIN_CLOCK	184320000
+#define AT91C_MASTER_CLOCK	46080000	/* peripheral clock (AT91C_MAIN_CLOCK / 4) */
+#define AT91C_SLOW_CLOCK	32768		/* slow clock */
+#define AT91_PLLB_INIT		0x128a3e19	/* (3.6864 * (650+1) / 25) /2 = 47.9969 */
+
+/* FLASH */
+#define AT91_FLASH_BASE		0x10000000	// NCS0: Flash physical base address
+
+/* SDRAM */
+#define AT91_SDRAM_BASE		0x20000000	// NCS1: SDRAM physical base address
+
+/* Multi-Master Memory controller */
+#define AT91_UHP_BASE		0x00300000	// USB Host controller
+
+
+/* Peripheral interrupt configuration */
+#define AT91_SMR_FIQ	(AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (FIQ)
+#define AT91_SMR_SYS	(AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// System Peripheral
+#define AT91_SMR_PIOA	(AT91C_AIC_PRIOR_LOWEST	 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller A
+#define AT91_SMR_PIOB	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller B
+#define AT91_SMR_PIOC	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller C
+#define AT91_SMR_PIOD	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Parallel IO Controller D
+#define AT91_SMR_US0	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 0
+#define AT91_SMR_US1	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 1
+#define AT91_SMR_US2	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 2
+#define AT91_SMR_US3	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USART 3
+#define AT91_SMR_MCI	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Multimedia Card Interface
+#define AT91_SMR_UDP	(AT91C_AIC_PRIOR_4       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USB Device Port
+#define AT91_SMR_TWI	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Two-Wire Interface
+#define AT91_SMR_SPI	(AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Peripheral Interface
+#define AT91_SMR_SSC0	(AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Synchronous Controller 0
+#define AT91_SMR_SSC1	(AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Synchronous Controller 1
+#define AT91_SMR_SSC2	(AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Serial Synchronous Controller 2
+#define AT91_SMR_TC0	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 0
+#define AT91_SMR_TC1	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 1
+#define AT91_SMR_TC2	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 2
+#define AT91_SMR_TC3	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 3
+#define AT91_SMR_TC4	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 4
+#define AT91_SMR_TC5	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Timer Counter 5
+#define AT91_SMR_UHP	(AT91C_AIC_PRIOR_3       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// USB Host port
+#define AT91_SMR_EMAC	(AT91C_AIC_PRIOR_3       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Ethernet MAC
+#define AT91_SMR_IRQ0	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ0)
+#define AT91_SMR_IRQ1	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ1)
+#define AT91_SMR_IRQ2	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ2)
+#define AT91_SMR_IRQ3	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ3)
+#define AT91_SMR_IRQ4	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ4)
+#define AT91_SMR_IRQ5	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ5)
+#define AT91_SMR_IRQ6	(AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)	// Advanced Interrupt Controller (IRQ6)
+
+
+#define AT91C_CONSOLE_DEFAULT_BAUDRATE 38400
+
+/*
+ * Serial port configuration.
+ *    0 .. 3 = USART0 .. USART3
+ *    4      = DBGU
+ */
+#define AT91C_UART_MAP		{ 4, 1, -1, -1, -1 }	/* ttyS0, ..., ttyS4 */
+#define AT91C_CONSOLE		0			/* ttyS0 */
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/debug-macro.S linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/debug-macro.S
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/debug-macro.S	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/debug-macro.S	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,36 @@
+/* 
+ * include/asm-arm/arch-at91rm9200/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <asm/hardware.h>
+
+	.macro	addruart,rx
+	mrc	p15, 0, \rx, c1, c0
+	tst	\rx, #1				@ MMU enabled?
+	ldreq	\rx, =AT91C_BASE_SYS		@ System peripherals (phys address)
+	ldrne	\rx, =AT91C_VA_BASE_SYS		@ System peripherals (virt address)
+	.endm
+
+	.macro	senduart,rd,rx
+	strb	\rd, [\rx, #DBGU_THR]		@ DBGU_THR
+	.endm
+
+	.macro	waituart,rd,rx
+1001:	ldr	\rd, [\rx, #DBGU_CSR]		@ DBGU_CSR
+	tst	\rd, #AT91C_DBGU_TXRDY		@ DBGU_TXRDY = 1 when ready to transmit
+	beq	1001b
+	.endm
+
+	.macro	busyuart,rd,rx
+1001:	ldr	\rd, [\rx, #DBGU_CSR]		@ DBGU_CSR
+	tst	\rd, #AT91C_DBGU_TXEMPTY	@ DBGU_TXEMPTY = 1 when transmission complete
+	beq	1001b
+	.endm
+
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/dma.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/dma.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/dma.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/dma.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,27 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/dma.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS		0xffffffff
+#define MAX_DMA_CHANNELS	0
+
+#endif /* _ASM_ARCH_DMA_H */
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/entry-macro.S linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/entry-macro.S
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/entry-macro.S	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/entry-macro.S	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,23 @@
+/*
+ * include/asm-arm/arch-at91rm9200/entry-macro.S
+ *
+ * Low-level IRQ helper macros for AT91RM9200 platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/hardware.h>
+
+	.macro	disable_fiq
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+	ldr	\base, =(AT91C_VA_BASE_SYS)	@ base virtual address of SYS peripherals
+	ldr	\irqnr, [\base, #AIC_IVR]	@ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
+	ldr	\irqstat, [\base, #AIC_ISR]	@ read interrupt source number
+	teq	\irqstat, #0			@ ISR is 0 when no current interrupt, or spurious interrupt
+	streq	\tmp, [\base, #AIC_EOICR]	@ not going to be handled further, then ACK it now.
+	.endm
+
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/hardware.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/hardware.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/hardware.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/hardware.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,94 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/hardware.h
+ *
+ *  Copyright (c) 2003 SAN People
+ *  Copyright (c) 2003 ATMEL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+#include <asm/arch/AT91RM9200.h>
+#include <asm/arch/AT91RM9200_SYS.h>
+
+#ifndef __ASSEMBLY__
+ /*
+  * The following variable is defined in arch/arm/mach-at91rm9200/core.c
+  * It is a pointer to the AT91RM9200 system peripherals.
+  */
+extern AT91PS_SYS AT91_SYS;
+#endif
+
+
+/*
+ * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
+ * to 0xFEFA0000 .. 0xFF000000.  (384Kb)
+ */
+#define AT91C_IO_PHYS_BASE	0xFFFA0000
+#define AT91C_IO_SIZE		(0xFFFFFFFF - AT91C_IO_PHYS_BASE + 1)
+#define AT91C_IO_VIRT_BASE	(0xFF000000 - AT91C_IO_SIZE)
+
+ /* Convert a physical IO address to virtual IO address */
+#define AT91_IO_P2V(x)	((x) - AT91C_IO_PHYS_BASE + AT91C_IO_VIRT_BASE)
+
+/*
+ * Virtual to Physical Address mapping for IO devices.
+ */
+#define AT91C_VA_BASE_SYS	AT91_IO_P2V(AT91C_BASE_SYS)
+#define AT91C_VA_BASE_SPI	AT91_IO_P2V(AT91C_BASE_SPI)
+#define AT91C_VA_BASE_SSC2	AT91_IO_P2V(AT91C_BASE_SSC2)
+#define AT91C_VA_BASE_SSC1	AT91_IO_P2V(AT91C_BASE_SSC1)
+#define AT91C_VA_BASE_SSC0	AT91_IO_P2V(AT91C_BASE_SSC0)
+#define AT91C_VA_BASE_US3	AT91_IO_P2V(AT91C_BASE_US3)
+#define AT91C_VA_BASE_US2	AT91_IO_P2V(AT91C_BASE_US2)
+#define AT91C_VA_BASE_US1	AT91_IO_P2V(AT91C_BASE_US1)
+#define AT91C_VA_BASE_US0	AT91_IO_P2V(AT91C_BASE_US0)
+#define AT91C_VA_BASE_EMAC	AT91_IO_P2V(AT91C_BASE_EMAC)
+#define AT91C_VA_BASE_TWI	AT91_IO_P2V(AT91C_BASE_TWI)
+#define AT91C_VA_BASE_MCI	AT91_IO_P2V(AT91C_BASE_MCI)
+#define AT91C_VA_BASE_UDP	AT91_IO_P2V(AT91C_BASE_UDP)
+#define AT91C_VA_BASE_TCB1	AT91_IO_P2V(AT91C_BASE_TCB1)
+#define AT91C_VA_BASE_TCB0	AT91_IO_P2V(AT91C_BASE_TCB0)
+
+
+#define AT91C_BASE_SRAM		0x00200000	/* Internal SRAM base address */
+#define AT91C_SRAM_SIZE		0x00004000	/* Internal SRAM SIZE (16Kb) */
+
+#define AT91C_NR_UART		5		/* 4 USART3's and one DBGU port */
+
+ /* Definition of interrupt priority levels */
+#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST
+#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1)
+#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2)
+#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3)
+#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4)
+#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5)
+#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6)
+#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST
+
+
+/*
+ * Implementation specific hardware definitions.
+ */
+
+#ifdef CONFIG_ARCH_AT91RM9200DK
+#include <asm/arch/at91rm9200dk.h>
+#endif
+
+#ifdef CONFIG_MACH_CSB337
+#include <asm/arch/csb337.h>
+#endif
+
+#ifdef CONFIG_MACH_CSB637
+#include <asm/arch/csb637.h>
+#endif
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/io.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/io.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/io.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/io.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,30 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/io.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT		0xFFFFFFFF
+
+#define __io(a)			(a)
+#define __mem_pci(a)		((unsigned long)(a))
+
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/irqs.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/irqs.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/irqs.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/irqs.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,37 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/irqs.h
+ *
+ *  Copyright (C) 2004 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define NR_IRQS 32
+
+/*
+ * Acknowledge interrupt with AIC after interrupt has been handled.
+ *   (by kernel/irq.c)
+ */
+#define irq_finish(irq) do { AT91_SYS->AIC_EOICR = 0; } while (0)
+
+/*
+ *  IRQ interrupts definitions are the same as the ID definitions
+ *  in AT91RM9200.h
+ */
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/memory.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/memory.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/memory.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/memory.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,41 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/memory.h
+ *
+ *  Copyright (C) 2004 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/arch/hardware.h>
+
+#define PHYS_OFFSET	(AT91_SDRAM_BASE)
+
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/param.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/param.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/param.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/param.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,28 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/param.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_PARAM_H
+#define __ASM_ARCH_PARAM_H
+
+/*
+ * We use default params
+ */
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/pio.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/pio.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/pio.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/pio.h	Fri Feb 25 12:55:39 2005
@@ -0,0 +1,165 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/pio.h
+ *
+ *  Copyright (c) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_PIO_H
+#define __ASM_ARCH_PIO_H
+
+#include <asm/arch/hardware.h>
+
+static inline void AT91_CfgPIO_USART0(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0
+		| AT91C_PA20_CTS0;
+
+	/*
+	 * Errata #39 - RTS0 is not internally connected to PA21.  We need to drive
+	 *  the pin manually.  Default is off (RTS is active low).
+	 */
+	AT91_SYS->PIOA_PER = AT91C_PA21_RTS0;
+	AT91_SYS->PIOA_OER = AT91C_PA21_RTS0;
+	AT91_SYS->PIOA_SODR = AT91C_PA21_RTS0;
+}
+
+static inline void AT91_CfgPIO_USART1(void) {
+	AT91_SYS->PIOB_PDR = AT91C_PB18_RI1 | AT91C_PB19_DTR1
+		| AT91C_PB20_TXD1 | AT91C_PB21_RXD1 | AT91C_PB23_DCD1
+		| AT91C_PB24_CTS1 | AT91C_PB25_DSR1 | AT91C_PB26_RTS1;
+}
+
+static inline void AT91_CfgPIO_USART2(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA22_RXD2 | AT91C_PA23_TXD2;
+}
+
+static inline void AT91_CfgPIO_USART3(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3;
+	AT91_SYS->PIOA_BSR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3;
+}
+
+static inline void AT91_CfgPIO_DBGU(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
+}
+
+/*
+ * Configure Ethernet for RMII mode.
+ */
+static inline void AT91_CfgPIO_EMAC_RMII(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1
+		| AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1
+		| AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | AT91C_PA7_ETXCK_EREFCK;
+}
+
+/*
+ * Configure Ethernet for MII mode.
+ */
+static inline void AT91_CfgPIO_EMAC_MII(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1
+		| AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1
+		| AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | AT91C_PA7_ETXCK_EREFCK;
+	AT91_SYS->PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV
+		| AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3
+		| AT91C_PB12_ETX2;
+	AT91_SYS->PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV
+		| AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3
+		| AT91C_PB12_ETX2;
+}
+
+/*
+ * Configure interrupt from Ethernet PHY.
+ */
+static inline void AT91_CfgPIO_EMAC_PHY(void) {
+	AT91_SYS->PMC_PCER = 1 << AT91C_ID_PIOC;	/* enable peripheral clock */
+#if defined(CONFIG_MACH_CSB337) || defined(CONFIG_MACH_CSB637)
+	AT91_SYS->PIOC_ODR = AT91C_PIO_PC2;
+#else
+	AT91_SYS->PIOC_ODR = AT91C_PIO_PC4;
+#endif
+}
+
+/*
+ * Enable the Two-Wire interface.
+ */
+static inline void AT91_CfgPIO_TWI(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+	AT91_SYS->PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+	AT91_SYS->PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK;		/* open drain */
+}
+
+/*
+ * Enable the Serial Peripheral Interface.
+ */
+static inline void AT91_CfgPIO_SPI(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA0_MISO | AT91C_PA1_MOSI | AT91C_PA2_SPCK;
+}
+
+static inline void AT91_CfgPIO_SPI_CS0(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA3_NPCS0;
+}
+
+static inline void AT91_CfgPIO_SPI_CS1(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA4_NPCS1;
+}
+
+static inline void AT91_CfgPIO_SPI_CS2(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA5_NPCS2;
+}
+
+static inline void AT91_CfgPIO_SPI_CS3(void) {
+	AT91_SYS->PIOA_PDR = AT91C_PA6_NPCS3;
+}
+
+/*
+ * Select the DataFlash card.
+ */
+static inline void AT91_CfgPIO_DataFlashCard(void) {
+	AT91_SYS->PIOB_PER = AT91C_PIO_PB7;
+	AT91_SYS->PIOB_OER = AT91C_PIO_PB7;
+	AT91_SYS->PIOB_CODR = AT91C_PIO_PB7;
+}
+
+/*
+ * Enable NAND Flash (SmartMedia) interface.
+ */
+static inline void AT91_CfgPIO_SmartMedia(void) {
+	/* enable PC0=SMCE, PC1=SMOE, PC3=SMWE, A21=CLE, A22=ALE */
+	AT91_SYS->PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
+	AT91_SYS->PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
+
+	/* Configure PC2 as input (signal READY of the SmartMedia) */
+	AT91_SYS->PIOC_PER = AT91C_PC2_BFAVD;	/* enable direct output enable */
+	AT91_SYS->PIOC_ODR = AT91C_PC2_BFAVD;	/* disable output */
+
+	/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
+	AT91_SYS->PIOB_PER = AT91C_PIO_PB1;	/* enable direct output enable */
+	AT91_SYS->PIOB_ODR = AT91C_PIO_PB1;	/* disable output */
+}
+
+static inline int AT91_PIO_SmartMedia_RDY(void) {
+	return (AT91_SYS->PIOC_PDSR & AT91C_PIO_PC2) ? 1 : 0;
+}
+
+static inline int AT91_PIO_SmartMedia_CardDetect(void) {
+	return (AT91_SYS->PIOB_PDSR & AT91C_PIO_PB1) ? 1 : 0;
+}
+
+/*
+ * Enable MCI (MMC and SD cards) interface - Slot A
+ */
+static inline void AT91_CfgPIO_MCISlotA(void) {
+	/* Enable port A 27, 28, 29 peripheral A (MCCK, MCCDA, MCDA0) */
+	AT91_SYS->PIOA_ASR = AT91C_PA27_MCCK | AT91C_PA28_MCCDA | AT91C_PA29_MCDA0;
+	AT91_SYS->PIOA_PDR = AT91C_PA27_MCCK | AT91C_PA28_MCCDA | AT91C_PA29_MCDA0;
+
+	/* Enable port B 3, 4, 5 peripheral B (MCDA1, MCDA2, MCDA3) */
+	AT91_SYS->PIOB_BSR = AT91C_PB3_MCDA1 | AT91C_PB4_MCDA2 | AT91C_PB5_MCDA3;
+	AT91_SYS->PIOB_PDR = AT91C_PB3_MCDA1 | AT91C_PB4_MCDA2 | AT91C_PB5_MCDA3;
+}
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/platform.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/platform.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/platform.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/platform.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,42 @@
+#ifndef __ASM_ARCH_PLATFORM_H
+#define __ASM_ARCH_PLATFORM_H
+
+#include <linux/device.h>
+
+
+#ifdef CONFIG_USB_OHCI_HCD
+
+/* USB Host Controller */
+
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = 0xffffffffUL;
+
+static struct resource at91rm9200_usbh_resource[] = {
+	{
+		.start	= AT91_UHP_BASE,
+		.end	= AT91_UHP_BASE + SZ_1M,
+		.flags	= IORESOURCE_MEM
+	}
+}; 
+
+static struct platform_device at91rm9200_usbh_device = {
+	.name		= "at91rm9200-ohci",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(at91rm9200_usbh_resource),
+	.resource	= at91rm9200_usbh_resource,
+	.dev		= {
+				.dma_mask		= &ohci_dmamask,
+				.coherent_dma_mask	= 0xffffffff,
+			  }
+};
+#endif
+
+
+static struct platform_device *at91rm9200_devices[] __initdata = {
+#if defined (CONFIG_USB_OHCI_HCD)
+	&at91rm9200_usbh_device
+#endif
+};
+
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/system.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/system.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/system.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/system.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,51 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/system.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/hardware.h>
+
+static inline void arch_idle(void)
+{
+	/*
+	 * Disable the processor clock.  The processor will be automatically
+	 * re-enabled by an interrupt or by a reset.
+	 */
+//	AT91_SYS->PMC_SCDR = AT91C_PMC_PCK;
+
+	/*
+	 * Set the processor (CP15) into 'Wait for Interrupt' mode.
+	 * Unlike disabling the processor clock via the PMC (above)
+	 *  this allows the processor to be woken via JTAG.
+	 */
+	cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+	/*
+	 * Perform a hardware reset with the use of the Watchdog timer.
+	 */
+	AT91_SYS->ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
+	AT91_SYS->ST_CR = AT91C_ST_WDRST;
+}
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/timex.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/timex.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/timex.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/timex.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,26 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/timex.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#define CLOCK_TICK_RATE		(AT91C_SLOW_CLOCK)
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/uncompress.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/uncompress.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/uncompress.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/uncompress.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,55 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/uncompress.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/arch/hardware.h>
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+	AT91PS_SYS pSYS = (AT91PS_SYS) AT91C_BASE_SYS;	/* physical address */
+
+	while (*s) {
+		while (!(pSYS->DBGU_CSR & AT91C_DBGU_TXRDY)) { barrier(); }
+		pSYS->DBGU_THR = *s;
+		if (*s == '\n')	{
+			while (!(pSYS->DBGU_CSR & AT91C_DBGU_TXRDY)) { barrier(); }
+			pSYS->DBGU_THR = '\r';
+		}
+		s++;
+	}
+	/* wait for transmission to complete */
+	while (!(pSYS->DBGU_CSR & AT91C_DBGU_TXEMPTY)) { barrier(); }
+}
+
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/vmalloc.h linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/vmalloc.h
--- linux-2.6.11-rc5.orig/include/asm-arm/arch-at91rm9200/vmalloc.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/arch-at91rm9200/vmalloc.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,37 @@
+/*
+ * linux/include/asm-arm/arch-at91rm9200/vmalloc.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+
+#define VMALLOC_OFFSET		(8*1024*1024)
+#define VMALLOC_START		(((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END		(AT91C_IO_VIRT_BASE-1)
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/asm-arm/mach/serial_at91rm9200.h linux-2.6.11-rc5/include/asm-arm/mach/serial_at91rm9200.h
--- linux-2.6.11-rc5.orig/include/asm-arm/mach/serial_at91rm9200.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/asm-arm/mach/serial_at91rm9200.h	Fri Feb 25 11:55:46 2005
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/mach/serial_at91rm9200.h
+ *
+ *  Based on serial_sa1100.h  by Nicolas Pitre
+ *
+ *  Copyright (C) 2002 ATMEL Rousset
+ *
+ *  Low level machine dependent UART functions.
+ */
+#include <linux/config.h>
+
+struct uart_port;
+
+/*
+ * This is a temporary structure for registering these
+ * functions; it is intended to be discarded after boot.
+ */
+struct at91rm9200_port_fns {
+	void	(*set_mctrl)(struct uart_port *, u_int);
+	u_int	(*get_mctrl)(struct uart_port *);
+	void	(*enable_ms)(struct uart_port *);
+	void	(*pm)(struct uart_port *, u_int, u_int);
+	int	(*set_wake)(struct uart_port *, u_int);
+	int	(*open)(struct uart_port *);
+	void	(*close)(struct uart_port *);
+};
+
+#if defined(CONFIG_SERIAL_AT91)
+void at91_register_uart_fns(struct at91rm9200_port_fns *fns);
+void at91_register_uart(int idx, int port);
+#else
+#define at91_register_uart_fns(fns) do { } while (0)
+#define at91_register_uart(idx,port) do { } while (0)
+#endif
+
+
diff -urN linux-2.6.11-rc5.orig/include/linux/at91_spi.h linux-2.6.11-rc5/include/linux/at91_spi.h
--- linux-2.6.11-rc5.orig/include/linux/at91_spi.h	Thu Jan  1 02:00:00 1970
+++ linux-2.6.11-rc5/include/linux/at91_spi.h	Fri Feb 25 11:55:47 2005
@@ -0,0 +1,56 @@
+/*
+ * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200
+ *
+ * (c) SAN People (Pty) Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef AT91_SPI_H
+#define AT91_SPI_H
+
+/* Maximum number of buffers in a single SPI transfer.
+ *  DataFlash uses maximum of 2
+ *  spidev interface supports up to 8.
+ */
+#define MAX_SPI_TRANSFERS	8
+
+#define NR_SPI_DEVICES  	4	/* number of devices on SPI bus */
+
+#define DATAFLASH_CLK		6000000
+#define DEFAULT_SPI_BAUD	AT91C_MASTER_CLOCK / (2 * DATAFLASH_CLK)
+
+#define SPI_MAJOR		153	/* registered device number */
+
+/*
+ * Describes the buffers for a SPI transfer.
+ * A transmit & receive buffer must be specified for each transfer
+ */
+struct spi_transfer_list {
+	void* tx[MAX_SPI_TRANSFERS];	/* transmit */
+	int txlen[MAX_SPI_TRANSFERS];
+	void* rx[MAX_SPI_TRANSFERS];	/* receive */
+	int rxlen[MAX_SPI_TRANSFERS];
+	int nr_transfers;		/* number of transfers */
+	int curr;			/* current transfer */
+};
+
+struct spi_local {
+	unsigned int pcs;		/* Peripheral Chip Select value */
+	short pio_enabled;		/* has PIO been enabled? */
+
+	struct spi_transfer_list *xfers;	/* current transfer list */
+	dma_addr_t tx, rx;		/* DMA address for current transfer */
+	dma_addr_t txnext, rxnext;	/* DMA address for next transfer */
+};
+
+
+/* Exported functions */
+extern void spi_access_bus(short device);
+extern void spi_release_bus(short device);
+extern int spi_transfer(struct spi_transfer_list* list);
+
+#endif
diff -urN linux-2.6.11-rc5.orig/include/linux/serial_core.h linux-2.6.11-rc5/include/linux/serial_core.h
--- linux-2.6.11-rc5.orig/include/linux/serial_core.h	Fri Feb 25 11:51:56 2005
+++ linux-2.6.11-rc5/include/linux/serial_core.h	Fri Feb 25 11:55:47 2005
@@ -67,6 +67,9 @@
 /* Parisc type numbers. */
 #define PORT_MUX	48
 
+/* Atmel AT91RM9200 SoC */
+#define PORT_AT91RM9200 49
+
 /* Macintosh Zilog type numbers */
 #define PORT_MAC_ZILOG	50	/* m68k : not yet implemented */
 #define PORT_PMAC_ZILOG	51
